IP Library › Granted Patent US 8,865,598
Granted Patent B2
US 8,865,598 · App. 14/094,473 · Granted Oct 21, 2014

Method for positioning spacers in pitch multiplication

Inventors: Sanket Sant (Plano, TX); Gurtej Sandhu (Boise, ID); Neal R. Rueger (Boise, ID)
Assignee: Micron Technology, Inc.
H01L21/0337H01L27/1052H01L21/3086H01L21/3088
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Quick Facts
Patent No.
US 8,865,598
App. No.
14/094,473
Granted
Oct 21, 2014
Kind
B2
Abstract

Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.

Claims (61)

1. A method for forming an integrated circuit, comprising:

forming a first plurality of mandrels on a first level over a substrate;

forming a first plurality of spacers on sidewalls of the first plurality of mandrels;

forming a second plurality of mandrels on a second level over the first level;

forming a second plurality of spacers on the sidewalls of the second plurality of mandrels, the second plurality of spacers elongated generally parallel to the first plurality of spacers;

selectively etching portions of material between spacers of each of the first and the second pluralities of spacers to form a pattern defined by spacers of the first and the second pluralities of spacers; and

transferring the pattern to the substrate, wherein transferring the pattern to the substrate comprises:

transferring the pattern to an amorphous carbon layer; and

subsequently etching the pattern into the substrate.

2. The method of claim 1 , wherein forming the first plurality of mandrels comprises patterning a carbon-containing layer to define the first plurality of mandrels in the carbon-containing layer.

3. The method of claim 2 , wherein the carbon-containing layer is formed of amorphous carbon.

4. The method of claim 1 , wherein forming the first plurality of spacers comprises:

blanket depositing a layer of spacer material on the first plurality of mandrels; and

anisotropically etching the layer of spacer material to define the first plurality of spacers.

5. The method of claim 4 , wherein forming the second plurality of mandrels comprises:

depositing a planarization layer around the first plurality of spacers;

depositing a carbon-containing layer on the planarization layer; and

patterning the carbon-containing layer to define the second plurality of mandrels.

6. The method of claim 4 , wherein forming the second plurality of spacers comprises:

blanket depositing a layer of spacer material on the second plurality of mandrels; and

anisotropically etching the layer of spacer material to define the second plurality of spacers.

7. The method of claim 6 , further comprising selectively removing alternating ones of the second plurality of spacers.

8. The method of claim 1 , wherein selectively etching portions of material between spacers comprises:

selectively removing the second plurality of mandrels, thereby exposing portions of the material between spacers of the first plurality of spacers; and

anisotropically etching the exposed portions of the material between spacers of the first plurality of spacers.

9. A method for forming an integrated circuit, comprising:

sequentially forming spacers on first and second levels, the spacers on the first level elongated generally parallel to the spacers on the second level;

selectively removing material between the spacers of the first and second levels to form a pattern defined by the spacers on the first and second levels, wherein the material comprises amorphous carbon; and

transferring the pattern to a substrate.

10. The method of claim 9 , further comprising forming spacers on a third level above the first and second levels.

11. The method of claim 9 , wherein sequentially forming spacers on the first and second levels comprises:

forming free-standing spacers on the first level;

depositing a planarization layer around the free-standing spacers on the first level; and

forming the spacers of the second level over the planarization layer.

12. The method of claim 9 , wherein transferring the pattern to the substrate comprises:

etching the pattern into a hardmask layer;

subsequently removing the spacers on the first and second levels; and

patterning the substrate through the hardmask layer.

13. The method of claim 9 , wherein selectively removing comprises:

etching exposed material between the spacers on the second level to expose material between spacers on the first level; and

etching the exposed material separating the spacers on the first level.

14. A method for forming an integrated circuit, comprising:

forming a mask comprising a pattern, the mask comprising:

spacers on an upper level;

trimming the spacers on the upper level; and

spacers on a lower level, the spacers on the lower and upper levels elongated in a same direction; and

etching the pattern into a substrate.

15. The method of claim 14 , wherein forming the mask comprises forming the spacers on the upper level laterally off-set from the spacers on the lower level.

16. The method of claim 14 wherein trimming the spacers on the upper level comprises performing an isotropic etch.

17. The method of claim 14 , wherein forming the mask comprises:

transferring the pattern to a hard mask layer underlying the lower level; and

subsequently removing the mask,

wherein etching the pattern into the substrate comprises etching the substrate through the mask.

18. The method of claim 14 , wherein etching the pattern into a substrate comprises etching a semiconductor material.

19. A method for forming an integrated circuit, comprising:

forming a first plurality of mandrels on a first level over a substrate, wherein forming the first plurality of mandrels comprises patterning a carbon-containing layer to define the first plurality of mandrels in the carbon-containing layer, wherein the carbon-containing layer is formed of amorphous carbon;

forming a first plurality of spacers on sidewalls of the first plurality of mandrels;

forming a second plurality of mandrels on a second level over the first level;

forming a second plurality of spacers on the sidewalls of the second plurality of mandrels, the second plurality of spacers elongated generally parallel to the first plurality of spacers;

selectively etching portions of material between spacers of each of the first and the second pluralities of spacers to form a pattern defined by spacers of the first and the second pluralities of spacers; and

transferring the pattern to the substrate.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (5)
Continuation 13447520 · Apr 16, 2012
Continuation 13179851 · Jul 11, 2011
Division 12489337 · Jun 22, 2009
Division 11144543 · Jun 2, 2005
Related Publication 20140087563A1 · Mar 27, 2014