Semiconductor device and manufacture method thereof
View Patent ↗A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well region disposed in a substrate, a gate disposed on the substrate, a halo region disposed in a channel region under the gate, and a source LDD region and a drain LDD region disposed on opposite sides of the halo region.
1. A semiconductor device, comprising:
a well region disposed in a substrate;
a gate disposed on the substrate;
a halo region disposed in a channel region under the gate; and
a source LDD region and a drain LDD region disposed on opposite sides of the halo region,
wherein the halo region is spaced apart from the source LDD region and the drain LDD region, and is disposed substantially at a center of the channel region under the gate.
2. The semiconductor device of claim 1 , wherein the halo region and the well region are doped with the same-type dopant, and the source LDD region and the drain LDD region are doped with dopants different from the type of dopants for the halo region and the well region.
3. The semiconductor device of claim 2 , wherein the halo region comprises an area having a higher doping concentration than the well region.
4. The semiconductor device of claim 2 , wherein the halo region has a greater depth from the surface of the substrate than the source LDD region and the drain LDD region.
5. The semiconductor device of claim 2 , wherein the halo region has a shorter length than the gate.
6. The semiconductor device of claim 2 , wherein distances between the halo region and edges of the gate are substantially the same on both sides of the halo region.
7. The semiconductor device of claim 6 , wherein the distances range between 0.025 μm and 0.155 μm.
8. The semiconductor device of claim 6 , wherein the distances decrease as a length of the halo region increases.
9. The semiconductor device of claim 8 , wherein, as a length of the halo region decreases, a threshold voltage decreases and a drain saturation current increases.
10. The semiconductor device of claim 1 , wherein the halo region comprises two peak concentration areas between a surface of the substrate and a depth of 0˜0.1 μm from the surface of the substrate.
11. The semiconductor device of claim 10 , wherein the first peak concentration area of the two peak concentration areas is disposed in a vicinity of the surface of the substrate.
12. The semiconductor device of claim 10 , wherein the second peak concentration area of the two peak concentration areas is disposed between the surface of the substrate and a depth of 0.05˜0.1 μm from the surface of the substrate.
13. The semiconductor device of claim 1 , further comprising:
a source junction region adjoined with the source LDD region;
a drain junction region adjoined with the drain LDD region; and
an isolation adjoined with the source junction region or the drain junction region, wherein the source junction region or the drain junction region and the isolation are disposed in the well region.
14. The semiconductor device of claim 1 , wherein the gate further comprises: a gate oxide layer and a poly gate layer disposed on an upper surface of the substrate above the halo region and above a part of the source LDD region and a part of the drain LDD region; and spacers on sides of the gate oxide layer and the poly gate layer.
15. A semiconductor device, comprising:
a well region disposed in a substrate;
a gate disposed on the substrate;
a halo region disposed in a channel region under the gate; and
a source LDD region and a drain LDD region disposed on opposite sides of the halo region, wherein the halo region and the well region are doped with the same-type dopant, and the source LDD region and the drain LDD region are doped with dopants different from the type of dopants for the halo region and the well region; and the halo region is disposed substantially at a center of the channel region under the gate, and the channel region including the halo region disposed therein has a higher doping concentration at the center than both sides.
16. The semiconductor device of claim 15 , wherein the halo region has a peak concentration in a range of 10 17-18 /cm 3 between a surface of the substrate and a depth of 0˜0.2 μm from the surface of the substrate.
17. A method for manufacturing a semiconductor device, comprising:
forming a halo region in a well region of a substrate;
forming a gate on an upper surface of the substrate above the halo region; and
forming a source LDD region and a drain LDD region on opposite sides to the halo region such that the source LDD region and the drain LDD region are spaced apart from the halo region,
wherein tie halo region is formed substantially at a center of the channel region under the gate.
18. The method of claim 17 , wherein the halo region is formed by ion implantation applied vertically from the upper surface of the substrate.
19. The method of claim 18 , wherein the halo region is formed with a tilt angle of 0°.
20. The method of claim 17 , wherein the source LDD region and the drain LDD region are formed by ion implantation on opposite sides of the gate, with a tilt.
21. The method of claim 17 , further comprising forming a source junction region on a side of the source LDD region and a drain junction region on a side of the drain LDD region.
22. The method of claim 17 , wherein the forming of the gate comprises:
forming a gate oxide layer;
forming a poly gate layer on the gate oxide layer; and
forming spacers on opposite sides of the gate oxide layer and the poly gate layer.