Semiconductor power device and method of fabricating the same

1. A semiconductor power device comprising:

a first conductivity type semiconductor substrate;

an epitaxial layer formed on the semiconductor substrate;

a second conductivity type well formed in the semiconductor;

a drain region formed in the well;

an oxide layer that insulates a gate region from the drain region;

a first conductivity type buried layer formed in the well;

a second conductivity type drift region surrounding the buried layer along at least a lateral side and a bottom side of the buried layer, the drift region disposed in the well; and

a second conductivity type TOP region formed between the buried layer and the oxide layer.

2. The semiconductor power device according to claim 1 , comprising a plurality of buried layers and a plurality of drift regions, the plurality of drift regions each surrounding a buried layer of the plurality of buried layers,

wherein the plurality of buried layers are spaced apart from each other along a vertical direction below the oxide layer, and the plurality of drift regions partially overlap with each other.

3. The semiconductor power device according to claim 1 , wherein the epitaxial layer is a first conductivity type epitaxial layer;

the drift region completely encloses the buried layer; and

the TOP region is formed in a region between the oxide layer and the buried layer and extends toward the gate region in a horizontal direction.

4. The semiconductor power device according to claim 1 , wherein the oxide layer includes one selected from the group consisting of a local oxidation of silicon (LOCOS) oxide layer, a plate-shaped oxide layer, and a shallow trench isolation (STI) layer.

5. The semiconductor power device according to claim 1 , further comprising a first conductivity type body region formed in a portion of the epitaxial layer in which the well is not formed.

6. The semiconductor power device according to claim 1 ,

wherein the drain region is formed in a trench structure.

7. The semiconductor power device according to claim 6 ,

wherein the drain region contacts one end of the drift region and one end of the buried layer.

8. The semiconductor power device according to claim 1 , comprising a plurality of epitaxial layers, the first conductivity type epitaxial layer being one of the plurality of epitaxial layers.

9. The semiconductor power device according to claim 1 , wherein the drift region has an ion implantation concentration higher than that of the well.

10. The semiconductor power device according to claim 1 , wherein the well contacts the TOP region.

11. The semiconductor power device according to claim 1 , wherein the well has a depth deeper than that of the epitaxial layer.

12. A semiconductor power device comprising:

a first conductivity type semiconductor substrate;

a second conductivity type epitaxial layer formed on the semiconductor substrate;

a second conductivity type well formed in the semiconductor substrate;

a drain region formed in the well;

an oxide layer that insulates a gate region from the drain region;

a first conductivity type first buried layer formed in the well;

a first conductivity type second buried layer formed on the semiconductor substrate in which the well is not formed;

a second conductivity type first drift region surrounding the first buried layer along at least a lateral side and a bottom side of the first buried layer, the drift region disposed in the well; and

a second conductivity type TOP region formed between the first buried layer and the oxide layer.

13. The semiconductor power device according to claim 12 , comprising a plurality of first buried layers and a plurality of first drift regions, the plurality of first drift regions each surrounding the first buried layer of the plurality of first buried layers,

wherein the plurality of first buried layers are spaced apart from each other along a vertical direction below the oxide layer, and the plurality of first drift regions partially overlap with each other.

14. The semiconductor power device according to claim 12 , wherein the first drift region completely encloses the first buried layer, and

the TOP region is formed in a channel between the oxide layer and the first buried layer and extends toward the gate region in a horizontal direction.

15. The semiconductor power device according to claim 12 , comprising a plurality of second buried layers, the plurality of second buried layers being spaced apart from each other along a vertical direction.

16. The semiconductor power device according to claim 12 , wherein the oxide layer includes one selected from the group consisting of a local oxidation of silicon (LOCOS) oxide layer, a plate-shaped oxide layer, and a shallow trench isolation (STI) layer.

17. The semiconductor power device according to claim 12 , further comprising a first conductivity type body region formed on the semiconductor substrate in which the well is not formed.

18. The semiconductor power device according to claim 12 , wherein the drain region is formed in a trench structure,

wherein the drain region contacts one end of the first drift region and one end of the first buried layer.

19. The semiconductor power device according to claim 12 , comprising a plurality of epitaxial layers, the second conductivity type epitaxial layer being one of the plurality of epitaxial layers.

20. The semiconductor power device according to claim 12 , wherein the drift region has an ion implantation concentration higher than that of the well.

21. The semiconductor power device according to claim 12 , wherein the well contacts the TOP region.

22. The semiconductor power according to claim 12 , wherein the well has a depth deeper than that of the epitaxial layer.