Non-volatile memory systems and methods
View Patent ↗A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
1. A system comprising:
one or more circuits configured for programming a multilevel memory cell, the one or more circuits including transistors arranged and electrically coupled to:
determine whether a read margin of said memory cell matches a certain criteria;
determine data corresponding to content of a read memory cell; and
allow access to said memory cell.
2. The system of claim 1 wherein the system is configured to:
process upper program margin verify voltages; and
compare the upper program margin verify voltages with read back cell voltages to determine whether to end the page programming sequence for a current page.
3. The system of claim 1 further configured to:
process lower program margin verify voltages; and
compare the lower program margin verify voltages with read back cell voltages to determine whether to end the page programming sequence for a current page.
4. The system of claim 1 wherein the system is configured to enter an upper margin verify mode.
5. The system of claim 1 wherein the system is configured to enter a lower margin verify mode.
6. The system of claim 1 wherein the system is configured to:
apply an erase algorithm programmed via fuses upon one selected erase block of memory cells at a time.
7. The system of claim 6 wherein erase blocks include a plurality of pages of memory cells.
8. The system of claim 6 wherein quantities of pages within the erase blocks are programmable via fuses for different user requirements and/or applications.
9. The system of claim 1 wherein the system is configured to:
apply a read algorithm programmed via fuses upon one selected page of memory cells at a time.
10. The system of claim 9 wherein quantities of memory cells within a page is programmable via fuses to optimize power consumption and/or data rate.
11. The system of claim 1 wherein the system is configured to:
autozero an input and output in order to zero out offset in an amplifier.
12. The system of claim 1 wherein the system is configured to:
capacitively sense an output of a memory cell via selective coupling of the reference sense amplifier to one or more reference memory subarrays.
13. The system of claim 1 wherein the system is configured to:
selectively couple a reference sense amplifier to a group of sense amplifiers to capacitively sense an output associated with the group of sense amplifiers.
14. The system of claim 1 wherein the system is configured to:
couple a reference array to reference memory subarrays; and
provide stored reference signals used for reading reference memory cells, the stored reference signals corresponding to detected reference signals.
15. A method of reading and/or programming a multilevel memory cell, the method comprising:
determining whether a read margin of said memory cell matches a certain criteria;
determining data corresponding to content of a read memory cell; and
allowing access to said memory cell.
16. The method of claim 15 further comprising:
processing upper program margin verify voltages; and
comparing the upper program margin verify voltages with read back cell voltages to determine whether to end a page programming sequence for a current page.
17. The method of claim 15 further comprising:
processing lower program margin verify voltages; and
comparing the lower program margin verify voltages with read back cell voltages to determine whether to end a page programming sequence for a current page.
18. The method of claim 15 further comprising entering an upper margin verify mode.
19. The method of claim 15 further comprising entering a lower margin verify mode.
20. The method of claim 15 further comprising:
applying an erase algorithm programmed via fuses upon one selected erase block of memory cells at a time.
21. The method of claim 20 wherein erase blocks include a plurality of pages of memory cells.
22. The method of claim 20 wherein quantities of pages within the erase blocks are programmable via fuses for different user requirements and/or applications.
23. The method of claim 15 further comprising:
applying a read algorithm programmed via fuses upon one selected page of memory cells at a time.
24. The method of claim 23 wherein quantities of memory cells within a page is programmable via fuses to optimize power consumption and/or data rate.
25. The method of claim 15 further comprising:
autozeroing an input and output in order to zero out offset in an amplifier.
26. The method of claim 15 further comprising:
capacitively sensing an output of a memory cell via selective coupling of the reference sense amplifier to one or more reference memory subarrays.
27. The method of claim 15 further comprising:
selectively coupling a reference sense amplifier to a group of sense amplifiers to capacitively sense an output associated with the group of sense amplifiers.
28. The method of claim 15 further comprising:
coupling a reference array to reference memory subarrays; and
providing stored reference signals used for reading reference memory cells, the stored reference signals corresponding to detected reference signals.