Packaging substrate and method for manufacturing same
A packaging substrate includes a first wiring layer, a first dielectric layer formed on the first wiring layer, a second wiring layer formed on the first dielectric layer, and a number of copper pillar bumps. Each copper pillar bump includes a base portion and a protruding portion. The base portion is connected to the first wiring layer, and the protruding portion is formed on the base portion. A size of the protruding portion is less than a size of the base portion, and a size of the copper pillar bump gradually increases from the protruding portion to the base portion.
1. A packaging substrate, comprising:
a first wiring layer;
a first dielectric layer formed on the first wiring layer;
a second wiring layer formed on the first dielectric layer;
a plurality of copper pillar bumps, each copper pillar bump comprising a base portion and a protruding portion; the base portion connected to the first wiring layer and portions of the first wiring layer exposed from the base portion, the protruding portion formed on the base portion; and
a first conductive layer formed on surfaces of the first wiring layer exposed from the base portion, and formed on surfaces of the base portion away from the first wiring layer, and formed on side surfaces of the base portion;
wherein a size of the protruding portion is less than a size of the base portion, and a size of the copper pillar bumps gradually increases from the protruding portion to the base portion.
2. The packaging substrate of claim 1 , wherein the first wiring layer is electrically connected to the second wiring layer via first conductive via-holes.
3. The packaging substrate of claim 1 , further comprising a second dielectric layer and a third wiring layer, wherein the second dielectric layer and the third wiring layer are orderly formed on the second wiring layer.
4. The packaging substrate of claim 3 , wherein the second wiring layer is electrically connected to the third wiring layer via second conductive via-holes.
5. The packaging substrate of claim 3 , wherein a solder masking layer is formed on the third wiring layer, parts of the third wiring layer exposing from the solder masking layer server as solder pads.