Flash memory device reducing layout area
View Patent ↗A flash memory device reducing a layout area is provided. In the flash memory device, even power transistors and odd power transistors of a plurality of power connection portions corresponding to a plurality of pairs of bit lines and even select transistors and odd select transistors of a plurality of select connection portions corresponding thereto are disposed in one common active region. In the flash memory device, since the number of insulation regions/layout areas for distinguishing active regions is reduced, a layout length in the vertical direction is reduced, ultimately reducing an entire required layout area considerably.
1. A flash memory device comprising:
a memory array;
a plurality of pairs of bit lines in communication with the memory array, each pair of bit lines comprising an even bit line and an odd bit line;
a plurality of common bit lines, each common bit line corresponding to one of the plurality of pairs of bit lines; and
a data transmission block in communication with the plurality of pairs of bit lines and the plurality of common bit lines to provide data extracted from the memory array by the plurality of pairs of bit lines to the common bit lines corresponding to the plurality of pairs of bit lines, the data transmission block comprising:
a plurality of power connection portions, each power connection portion in communication with one of the plurality of pairs of bit lines and comprising an even power transistor in communication with an even bit line of a given pair of bit lines and controlled to connect the even bit line to a power voltage and an odd power transistor in communication with an odd bit line of the given pair of bit lines and to connect the odd bit line to the power voltage;
a plurality of select connection portions configured, each select connection portion in communication with a given power connection portion and comprising an even select transistor in communication with an even bit line of the pair of bit lines associated with the given power connection and controlled to connect the associated even bit line to a given common bit line and an odd select transistor in communication with an odd bit line of the pair of bit lines associated with the given power connection and controlled to connect the associated odd bit line to the given common bit line; and
a single common active region comprising all even power transistors and odd power transistors of at least two of the plurality of power connection portions and all even select transistors and odd select transistors of the plurality of select connection portions.
2. The flash memory device of claim 1 , wherein the plurality of pairs of bit lines are formed using double patterning technology.
3. The flash memory device of claim 1 , wherein the single common active region further comprises:
power voltage wiring in communication with the power voltage;
even discharge signal wiring and odd discharge signal wiring in each one of the power connection portions in the single common active region, each even discharge signal wiring in communication with one of the even power transistors to gate that even power transistor and each odd discharge signal wiring in communication with one of the odd power transistors to gate that odd power transistor, the power voltage wiring disposed between even discharge signal wiring and odd discharge signal wiring pairs.
4. The flash memory device of claim 3 , wherein the single common active region further comprises:
even select signal wiring in communication with each even select transistor in the plurality of select connection portions to gate each even select transistor; and
odd select signal wiring in communication with each odd select transistor in the plurality of select connection portions to gate each odd select transistor, the even selection signal wiring and odd select wiring of a given select connection portion disposed between even discharge signal wiring odd discharge signal wiring of the given select connection portion.
5. The flash memory device of claim 1 , wherein each common bit line corresponding to a select connection portion disposed in the common active region is partially expanded and wired in a horizontal direction within the common action region and is expanded and wired in a vertical direction outside the common action region.
6. The flash memory device of claim 1 , wherein:
the plurality of pairs of bit lines are disposed in a first conductive layer; and
each pair of bit lines in communication with power connection portions disposed in the common active region comprising a portion disposed in a second conductive layer and expanded in a horizontal direction.
7. The flash memory device of claim 6 , wherein each common bit line is disposed in the second conductive layer.
8. The flash memory device of claim 1 , wherein the data transmission block further comprises:
at least one power active region comprising the even power transistor and the odd power transistor of a given power connection portion corresponding to a given pair of bit lines; and
at least one select active region comprising the even select transistor and the odd select transistor of a given select connection portion corresponding to the given power connection portion.
9. A flash memory device comprising:
a memory array;
a plurality of pairs of bit lines in communication with the memory array, each pair of bit lines comprising an even bit line and an odd bit line;
a plurality of common bit lines, each common bit line corresponding to one of the plurality of pairs of bit lines; and
a data transmission block in communication with the plurality of pairs of bit lines and the plurality of common bit lines to provide data extracted from the memory array by the plurality of pairs of bit lines to the common bit lines corresponding to the plurality of pairs of bit lines, the data transmission block comprising:
a plurality of power connection portions, each power connection portion in communication with one of the plurality of pairs of bit lines and comprising an even power transistor in communication with an even bit line of a given pair of bit lines and controlled to connect the even bit line to a power voltage and an odd power transistor in communication with an odd bit line of the given pair of bit lines and to connect the odd bit line to the power voltage;
a plurality of select connection portions configured, each select connection portion in communication with a given power connection portion and comprising an even select transistor in communication with an even bit line of the pair of bit lines associated with the given power connection and controlled to connect the associated even bit line to a given common bit line and an odd select transistor in communication with an odd bit line of the pair of bit lines associated with the given power connection and controlled to connect the associated odd bit line to the given common bit line; and
only three active regions, the three active regions comprising:
a single common active region comprising all even power transistors and odd power transistors of at least two of the plurality of power connection portions and all even select transistors and odd select transistors of the plurality of select connection portions;
a power active region comprising the even power transistor and the odd power transistor of a given power connection portion corresponding to a given pair of bit lines; and
a select active region comprising the even select transistor and the odd select transistor of a given select connection portion corresponding to the given power connection portion;
wherein the data transmission block comprises insulation regions only between active regions.