On-chip test for integrated AC coupling capacitors
Apparatus, method and computer program product for determining presence and relative magnitudes of on-chip AC coupling capacitors in a high-speed differential receiver device. A BIST method is employed to ultimately produce a dock count proportional to the fall time of a capacitor, and in the case of differential capacitors a difference in count values. Each capacitor path has a controllable first DAC current or voltage source. A second DAC current or voltage source, later in the data path and isolated from the capacitor node(s), is controlled to offset the voltage contribution of the charged and discharging capacitor. A count is recorded, starting when a capacitor charging current is shut off, and ends (the count) when the voltage of the charged capacitor falls below a threshold. A difference in count between the two data path capacitors is calculated and reported. A state machine operates the sequencing and control of the BIST.
1. A method of testing an on-chip coupling capacitor of an integrated circuit having an amplifier for receiving signals through the on-chip coupling capacitor, said method comprising:
a) setting said coupling capacitor to a fully charged state using a first current or voltage source (first source);
b) determining, using a second current or voltage source (second source) connected to an output of said amplifier on a data path isolated from said coupling capacitor, an offset voltage contribution of said coupling capacitor when in said charged state;
c) storing said determined offset voltage value in a memory storage device;
d) controlling a current or voltage supplied by said second source to a value sufficient to detect a coupling capacitor discharge state change at said isolated data path;
e) initiating a discharging state of said coupling capacitor, and initiating a counter device to begin a counting;
f) detecting when a signal representing said discharging state on said isolated data path has dropped below a threshold, and in response terminating counting by said counter device resulting in a count value; and
g) evaluating a status of said on-chip coupling capacitor based on the count value.
2. The method as claimed in claim 1 , wherein said status evaluating includes: processing said count value to estimate a magnitude of a capacitance of said on-chip coupling capacitor.
3. The method as claimed in claim 1 , wherein said monitoring includes receiving said output signal on said isolated data path as an input to a latch device, said latch device performing said detecting.
4. The method as claimed in claim 1 , wherein said amplifier is a differential amplifier receiving differential signals, said coupling capacitor is a first coupling capacitor configured to couple a first of said differential signals to said amplifier on a data path, said method further comprising:
repeating said a)-g) to determine a second count value for a second coupling capacitor, said second coupling capacitor configured to couple a second of said differential signals to said amplifier on said data path.
5. The method as claimed in claim 4 , further comprising:
checking if a difference between said count value determined for said first coupling capacitor and said second count value determined for said second coupling capacitor is within a predetermined count range.
6. The method as claimed in claim 1 , wherein said threshold is determined by said current or voltage supplied by said second source at a value reduced from a value of said second source setting when said offset voltage contribution of said coupling capacitor is detected.
7. The method as claimed in claim 6 , wherein said reduced value is a function of a prior determined static offset voltage value and said stored offset voltage value, said static offset voltage value being a static offset contribution of said amplifier.
8. The method as claimed in claim 7 , further comprising: predetermining said static offset voltage contribution of said amplifier by:
setting the first source connected to said coupling capacitor to an off state,
controlling setting of said second source to supply a minimum current or voltage to said isolated data path;
iteratively increasing said second source setting while monitoring a signal on said isolated data path until a change of voltage state at said isolated data path is detected, a setting of said second source at a time of said voltage state change corresponding to said static offset voltage; and
storing said determined static offset voltage value in the memory storage device.
9. The method as claimed in claim 1 , wherein said step b) of determining an offset voltage contribution of said coupling capacitor when in said charged state comprises:
controlling a setting of said second source to supply a minimum current or voltage to said isolated data path; and
iteratively increasing said second source setting while monitoring a signal on said isolated data path until a change of voltage state at said isolated data path is detected, a setting of said second source at a time of said voltage state change corresponding to said offset voltage contribution.
10. An apparatus for testing an on-chip coupling capacitor of an integrated circuit (IC) having an amplifier for receiving signals through the on-chip coupling capacitor, said apparatus comprising:
a first current or voltage source (first source) connected to a signal data path and configured for charging said on-chip coupling capacitor;
a second current or voltage source (second source) connected to an output of said amplifier at a data path isolated from said coupling capacitor and configured for supplying current or voltage to offset a data signal at an output of said amplifier;
an output latch for observing data state changes at an output of said amplifier; and
a logic processing circuit coupled with one or more memory storage devices, the processing circuit programmed to perform a method comprising:
a) charging the coupling capacitor to a fully charged state;
b) determining an offset voltage contribution of said coupling capacitor when in said fully charged state;
c) storing said determined offset voltage value in a storage device;
d) controlling said second source to supply current or voltage to a value sufficient to detect a coupling capacitor discharge state change at said isolated data path;
e) initiating a discharging state of said coupling capacitor by removing a current or voltage supplied by said first source, and initiating a counter device to begin a counting;
f) terminating counting by said counter device when said output latch detects a signal representing said capacitor discharging state on said isolated data path has dropped below a threshold, and obtaining a resulting count value; and
g) evaluating, using said logic processing circuit, a status of said on-chip coupling capacitor based on the count value.
11. The apparatus as claimed in claim 10 , wherein said evaluating by said logic processing circuit includes: processing said count value to estimate a magnitude of a capacitance of said on-chip coupling capacitor.
12. The apparatus as claimed in claim 10 , wherein said amplifier is a differential amplifier receiving differential signals, said coupling capacitor is a first coupling capacitor configured to couple a first of said differential signals to said amplifier on a data path, said method further comprising:
repeating said a)-g) to determine a second count value for a second coupling capacitor, said second coupling capacitor configured to couple a second of said differential signals to said amplifier on said data path.
13. The apparatus as claimed in claim 12 , further comprising:
a summation device connected to said amplifier output and configured for summing an amplifier output signal at said isolated data path with a current or voltage supplied by said second source.
14. The apparatus as claimed in claim 13 , wherein said output latch observes data state changes at an output of said summation device.
15. The apparatus as claimed in claim 12 , further comprising:
checking if a difference between said count value determined for said first coupling capacitor and said second count value determined for said second coupling capacitor is within a predetermined count range.
16. The apparatus as claimed in claim 10 , wherein said threshold corresponds to a setting of said second source at a value reduced from a value of said second source setting when said offset voltage contribution of said coupling capacitor is detected, said reduced value being a function of a prior determined static offset voltage value and said stored offset voltage value, said static offset voltage value being a static offset contribution of said amplifier.
17. The apparatus as claimed in claim 16 , wherein to predetermine said static offset voltage contribution of said amplifier, said method further comprises:
configuring said first source to turn off;
controlling, using said processing logic circuit, a setting of said second source to supply a minimum current or voltage to said isolated data path; and
iteratively increasing said second source setting while monitoring a signal on said isolated data path until a change of voltage state at said isolated data path is detected, a setting of said second source at a time of said voltage state change corresponding to said static offset voltage.
18. The apparatus as claimed in claim 10 , wherein to determine an offset voltage contribution of said coupling capacitor when in said charged state, said method comprises:
controlling a setting of said second source to supply a minimum current or voltage to said isolated data path; and
iteratively increasing said second source setting while monitoring a signal on said isolated data path until a change of voltage state at said isolated data path is detected, a setting of said second source at a time of said voltage state change corresponding to said offset voltage contribution.
19. A computer program product comprising:
a computer readable storage medium, said medium not a propagating signal, said medium tangibly embodying a program of instructions executable by the computer for testing an on-chip coupling capacitor of an integrated circuit having an amplifier for receiving signals through the on-chip coupling capacitor, said program of instructions, when executing, performing the following steps:
a) charging said coupling capacitor to a fully charged state using a first current or voltage source (first source);
b) determining, using a second current or voltage source (second source) connected to an output of said amplifier on a data path isolated from said coupling capacitor, an offset voltage contribution of said coupling capacitor when in said charged state;
c) storing said determined offset voltage value in a memory storage device;
d) controlling said second source to a value sufficient to detect coupling capacitor discharge state change at said isolated data path;
e) initiating a discharging state of said coupling capacitor by removing current or voltage supplied by said first source, and initiating a counter device to begin a counting;
f) terminating counting by said counter device when a signal representing said capacitor discharging state output on said isolated data path has dropped below a threshold, and obtaining a resulting count value; and
g) evaluating a status of said on-chip coupling capacitor based on the count value.
20. The computer program product as claimed in claim 19 , wherein said status evaluating includes: processing said count value to estimate a magnitude of a capacitance of said on-chip coupling capacitor.
21. The computer program product as claimed in claim 19 , wherein said monitoring includes receiving said output signal on said isolated data path as an input to a latch device, said latch device performing said detecting.
22. The computer program product as claimed in claim 19 , wherein said amplifier is a differential amplifier receiving differential signals, said coupling capacitor is a first coupling capacitor configured to couple a first of said differential signals to said amplifier on a data path, said method further comprising:
repeating said a)-g) to determine a second count value for a second coupling capacitor, said second coupling capacitor configured to couple a second of said differential signals to said amplifier on said data path.
23. The computer program product as claimed in claim 22 , further comprising:
checking if a difference between said count value determined for said first coupling capacitor and said second count value determined for said second coupling capacitor is within a predetermined count range.