IP Library › Granted Patent US 8,906,800
Granted Patent B2
US 8,906,800 · App. 14/164,352 · Granted Dec 9, 2014

Stacked digital/RF system-on-chip with integral isolation layer

Inventor: Neil David Feldman (Misgav, IL)
Assignee: Siano Mobile Silicon Ltd.
H04B1/10H01L23/5225H01L23/552H01L23/66H01L25/0657H01L24/82H04B1/08H01L25/18H01L2224/32225H01L2224/48227H01L2224/73265H01L2225/0651H01L2924/15311H01L2924/3025
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,906,800
App. No.
14/164,352
Granted
Dec 9, 2014
Kind
B2
Abstract

An apparatus includes a device package, a first Integrated Circuit (IC) that is packaged in the device package, and a second IC, which is packaged in the device package and is fabricated on a multi-layer interconnection circuit including a plurality of interconnection layers for interconnecting components of the second IC, wherein a selected layer in the plurality is configured to serve as a conductive shield for reducing interference between the first and second ICs.

Claims (10)

1. A method for reception, comprising:

receiving a Radio Frequency (RF) signal using a RF Integrated Circuit (RFIC) that is packaged in a device package; and

processing the received signal using a digital IC that is packaged together with the RFIC in the device package,

wherein one of the RFIC and the digital IC is fabricated on a multi-layer circuit substrate comprising a plurality of interconnection layers for interconnecting components of the one of the RFIC and the digital IC, and wherein a selected interconnection layer inside the multi-layer substrate is configured to serve as a conductive shield for reducing interference between the RFIC and the digital IC.

2. The method according to claim 1 , wherein receiving and processing the signal comprise receiving and processing a Mobile Digital Television (MDTV) signal.

3. The method according to claim 1 , wherein the interference comprises leakage of a clock signal, which is generated in the digital IC, into the RFIC.

4. The method according to claim 1 , wherein the selected interconnection layer is not used for interconnecting any of the components.

5. The method according to claim 1 , wherein the RFIC and the digital IC are stacked one on top of the other in the device package.

6. The method according to claim 1 , wherein the interconnection layers, including the selected interconnection layer, are formed jointly in a single fabrication process of the multi-layer substrate.

7. The method according to claim 6 , wherein the single fabrication process comprises a copper interconnect process.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2024
From: SHENZHEN XIN SINUO TECHNOLOGY PARTNERSHIP (LIMITED PARTNERSHIP)
To: XIN SINUO (NANJING) TECHNOLOGY CO., LTD.
Reel/Frame 069267/0374 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2022
From: CHI-JIA TECHNOLOGY CO., LTD.
To: SHENZHEN XIN SINUO TECHNOLOGY PARTNERSHIP (LIMITED PARTNERSHIP)
Reel/Frame 061784/0783 →
COURT ORDER Recorded May 2, 2017
From: SIANO MOBILE SILICON LTD.
To: CHI-JIA TECHNOLOGY CO., LTD.
Reel/Frame 042389/0153 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2014
From: FELDMAN, NEIL DAVID
To: SIANO MOBILE SILICON LTD.
Reel/Frame 032047/0803 →
Continuity (3)
Division 14027210 · Sep 15, 2013
Division 13014729 · Jan 27, 2011
Related Publication 20140140453A1 · May 22, 2014