Non-volatile FINFET memory device and manufacturing method thereof
Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers.
1. A method of fabricating an electronic device, comprising:
forming one or more masking layers on a semiconducting surface of a substrate;
forming a plurality of fin-type projections in said semiconducting surface based on said one or more masking layers; forming a plurality of dielectric isolation features based on said one or more masking layers; processing said masking layers and said plurality of fin-type projections to provide an inverted T-shaped cross-section for said plurality of fin-type projections comprising a distal extension portion and a proximal base portion, wherein said plurality of dielectric isolation features have a height being greater that a height of said proximal base portion of said plurality of fin-type projections; forming a plurality of dielectric layers on said distal extension portion, wherein a portion of said plurality of dielectric layers substantially fill a region that extends between a portion of a sidewall of said distal extension portion of said plurality of fin-type projections and a sidewall of said plurality of dielectric isolation features and that extends between said height of said proximal base portion and said height of said plurality of dielectric isolation features; and forming a plurality of gate layers on said plurality of dielectric isolation features and said plurality of dielectric layers.
2. The method of claim 1 , wherein said forming said plurality of dielectric isolation features further comprises:
processing said substrate to transfer a pattern defined by said one or more masking layers into said semiconducting surface to define said plurality of fin-type projections; and
forming a dielectric material between said plurality of fin-type projections to define said plurality of dielectric isolation features, wherein the height of said dielectric isolation features is less than a height of said plurality of fin-type projections.
3. The method of claim 1 , wherein said forming said dielectric isolation features further comprises:
selectively growing a dielectric material using said one or more masking layers to form said plurality of dielectric isolation features and said plurality of fin-type projections; and
selectively removing a portion of said plurality of dielectric isolation features such that the height of said dielectric isolation features is less than a height of said plurality of fin-type projections.
4. The method of claim 1 , wherein said processing further comprises:
reducing a width of at least a portion of said plurality of one or more masking features to form a second plurality of masking features;
transferring a pattern defined by said second plurality of masking features into said plurality of fin-type projections to form said distal extension portion.
5. The method of claim 1 , further comprising selecting a difference between said height of said dielectric isolation features and said height of said proximal base portion in said plurality of fin-type projections to be at least 100 angstroms.
6. The method of claim 1 , further comprising selecting a difference between said height of said dielectric isolation features and said height of said proximal base portion in said plurality of fin-type projections to be at most 1000 angstroms.
7. The method of claim 1 , further comprising:
processing said plurality of control gate layers to define a plurality of lines coextending in a second direction transverse to a first direction;
communicatively coupling a control element to said plurality of lines and a plurality of active areas to provide a memory system; and
forming an electronic system with said memory system.
8. The method of claim 1 , wherein the forming a plurality of dielectric layers comprises forming a tunnel oxide layer, a charge trapping layer, and a gate dielectric layer.
9. The method of claim 1 , wherein the forming a plurality of dielectric layers comprises removing a portion of the plurality of dielectric layers disposed over the dielectric isolation features.
10. The method of claim 1 , wherein the forming one or more masking layers comprises forming a layer of silicon dioxide and a layer of silicon nitride.