IP Library Patent Application 14189311
Patent Application
App. No. 14/189,311

IMAGE SENSORS HAVING PIXEL ARRAYS WITH NON-UNIFORM PIXEL SIZES

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Quick Facts
Patent No.
US None
App. No.
14/189,311
Abstract

An image sensor having an array of pixels and a silicon substrate may be provided. In one embodiment, the array of pixels may have pixels of equal charge storage capacity but with varying sizes and thus varying sensitivities. For example, a first pixel may have a larger charge-generating volume than a second pixel. In another suitable embodiment, the charge storage capacity of the image sensor pixels may be varied while the charge-generating volume remains the same. These configurations are achieved by placing a p+ type doped layer in the silicon substrate close to and parallel to the surface of the array. The p+ type doped layer may include a plurality of openings to allow photo-generated carriers to flow from the silicon bulk to the charge storage wells located near the surface of the substrate.

Claims (33)

1 . An image sensor having an array of image sensor pixels and a silicon substrate, the image sensor comprising:

a plurality of photodiodes formed in a surface of the silicon substrate, wherein the silicon substrate includes a bulk portion under the plurality of photodiodes;

a p+ type doped layer that extends under the plurality of photodiodes parallel to the surface, wherein the p+ type doped layer comprises a plurality of openings through which charge carriers pass from the bulk portion of the silicon substrate to the photodiodes; and

a plurality of pixel separation implants that separate the bulk portion of the silicon substrate into a plurality of charge-generating regions in which charge carriers are generated, wherein each photodiode collects charge carriers that are generated in a respective one of the charge-generating regions, and wherein at least two of the charge-generating regions have different sizes.

2 . The image sensor defined in claim 1 wherein the size of each charge-generating region is defined by the locations of the pixel separation implants.

3 . The image sensor defined in claim 2 wherein the plurality of photodiodes all have the same charge storage area.

4 . The image sensor defined in claim 2 wherein the at least two charge-generating regions comprise first and second charge-generating regions that correspond respectively to first and second image sensor pixels in the array of image sensor pixels, wherein the first image sensor pixel includes a color filter, and wherein the second image sensor pixel includes a broadband color filter.

5 . The image sensor defined in claim 4 wherein the first charge-generating region associated with the first image sensor is larger than the second charge-generating region associated with the second image sensor pixel.

6 . The image sensor defined in claim 4 wherein the first charge-generating region associated with the first image sensor pixel is smaller than the second charge-generating region associated with the second image sensor pixel.

7 . The image sensor defined in claim 2 wherein the at least two charge-generating regions comprise first and second charge-generating regions that correspond respectively to first and second image sensor pixels in the array of image sensor pixels, wherein the first image sensor pixel has a color filter corresponding to a primary color, and wherein the second image sensor pixel has a color filter corresponding to a complementary color.

8 . The image sensor defined in claim 7 wherein the first-charge generating region is larger than the second charge-generating region.

9 . The image sensor defined in claim 2 wherein the at least two charge-generating regions comprise first and second charge-generating regions that correspond respectively to first and second image sensor pixels in the array of image sensor pixels, wherein the first image sensor pixel has a rectangular shape, and wherein the second image sensor pixel has an octagonal shape.

10 . An image sensor having an array of image sensor pixels and a silicon substrate, the image sensor comprising:

a plurality of photodiodes formed in a surface of the silicon substrate, wherein the silicon substrate includes a bulk portion under the plurality of photodiodes and wherein at least two of the photodiodes have charge storage areas of different sizes;

a p+ type doped layer that extends under the plurality of photodiodes parallel to the surface, wherein the p+ type doped layer comprises a plurality of openings through which charge carriers pass from the bulk portion of the silicon substrate to the photodiodes; and

a plurality of pixel separation implants that separate the bulk portion of the silicon substrate into a plurality of charge-generating regions in which charge carriers are generated.

11 . The image sensor defined in claim 10 wherein each photodiode collects charge carriers that are generated in a respective one of the charge-generating regions.

12 . The image sensor defined in claim 11 wherein the charge-generating regions all have the same size.

13 . The image sensor defined in claim 10 wherein the at least two photodiodes comprise first and second photodiodes corresponding respectively to first and second image sensor pixels in the image sensor pixel array, wherein the first image sensor pixel includes a color filter, and wherein the second image sensor pixel includes a broadband color filter.

14 . The image sensor defined in claim 13 wherein the charge storage area of the first photodiode associated with the first image sensor pixel is smaller than the charge storage area of the second photodiode associated with the second image sensor pixel.

15 . A system, comprising:

a central processing unit;

memory;

input-output circuitry; and

an image sensor, wherein the image sensor includes an array of image sensor pixels and a silicon substrate, the image sensor comprising:

a plurality of photodiodes formed in a surface of the silicon substrate, wherein the silicon substrate includes a bulk portion under the plurality of photodiodes;

a p+ type doped layer that extends under the plurality of photodiodes parallel to the surface, wherein the p+ type doped layer comprises a plurality of openings through which charge carriers pass from the bulk portion of the silicon substrate to the photodiodes; and

a plurality of pixel separation implants that separate the bulk portion of the silicon substrate into a plurality of charge-generating regions in which charge carriers are generated, wherein each photodiode collects charge carriers that are generated in a respective one of the charge-generating regions, and wherein at least two of the charge-generating regions have different sizes.

16 . The system defined in claim 15 wherein the size of each charge-generating region is defined by the locations of the pixel separation implants.

17 . The system defined in claim 16 wherein the plurality of photodiodes all have the same charge storage area.

18 . The system defined in claim 16 wherein the at least two charge-generating regions comprise first and second charge-generating regions that correspond respectively to first and second image sensor pixels in the array of image sensor pixels, wherein the first image sensor pixel includes a color filter, and wherein the second image sensor pixel includes a broadband color filter.

19 . The system defined in claim 18 wherein the first charge-generating region associated with the first image sensor pixel is larger than the second charge-generating region associated with the second image sensor pixel.

20 . The system defined in claim 18 wherein the first charge-generating region associated with the first image sensor pixel is smaller than the second charge-generating region associated with the second image sensor pixel.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2014
From: APTINA IMAGING CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034673/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2014
From: HYNECEK, JAROSLAV
To: APTINA IMAGING CORPORATION
Reel/Frame 032294/0278 →