IP Library Granted Patent US 9,747,184
Granted Patent B2
US 9,747,184 · App. 14/219,043 · Granted Aug 29, 2017

Operation of I/O in a safe system

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Quick Facts
Patent No.
US 9,747,184
App. No.
14/219,043
Granted
Aug 29, 2017
Kind
B2
Abstract

A module health system includes a module health circuit comprising a hardware register that is set to a first value in response to the system starting, an application register that is set to the first value in response to the system starting and a watchdog timer register that is set to the first value in response to the system starting. The system further includes a power on self-test that determines whether the system has passed a plurality of tests and that selectively sets the hardware register to a second value based on the determination, an external software application that determines whether a safety critical system is healthy and selectively sets the application register based on the determination, a watchdog timer application that selectively sets the watchdog timer register, a central processing unit that determines whether to de-assert a module health signal.

Claims (25)

1. A module health system comprising:

a master CPU including:

a first module health circuit having:

a first hardware (HW) register that is set to a first value in response to the system starting;

a first application register that is set to the first value in response to the system starting;

a first watchdog (WD) timer register that is set to the first value in response to the system starting;

a first power on self-test (POST) that determines whether the master CPU has passed a plurality of tests and that selectively sets the first HW register to a second value based on the determination;

a first external software application that determines whether a safety critical system external to and associated with the module health system is healthy and selectively sets the first application register based on the determination;

a watchdog timer application that selectively sets the first WD timer register in response to receiving a watchdog signal; and

a first central processing unit (CPU) that determines whether to de-assert a first module health signal based on the values of the first HW register, the first application register, and the first WD timer register;

a checker CPU including:

a second module health circuit having:

a second hardware (HW) register that is set to a second value in response to the system starting;

a second application register that is set to the second value in response to the system starting;

a second watchdog (WD) timer register that is set to the second value in response to the system starting;

a second power on self-test (POST) that determines whether the checker CPU has passed a plurality of tests and that selectively sets the second HW register to a second value based on the determination;

a second external software application that determines whether the safety critical system is healthy and selectively sets the second application register based on the determination;

a watchdog timer application that selectively sets the second WD timer register in response to receiving a watchdog signal; and

a second central processing unit (CPU) that determines whether to de-assert a second module health signal based on the values of the second HW register, the second application register, and the second WD timer register

wherein the master CPU and the checker CPU each output respective health signals, and the respective health signals are compared to determine whether the module health system is operating properly.

2. The system of claim 1 wherein the first POST sets the first HW register to the second value when the first POST determines the master CPU passed the plurality of tests.

3. The system of claim 1 wherein the first POST does not set the first HW register to the second value when the first POST determines the master CPU did not pass at least one of the plurality of tests.

4. The system of claim 1 wherein the first software application sets the first application register to the second value when the first software application determines the safety critical system is healthy.

5. The system of claim 4 wherein the first software application and the second software application are same.

6. The system of claim 1 wherein the first software application and the second software application are same.

Assignments (9)
PATENT SECURITY AGREEMENT Recorded Jun 30, 2025
From: CREELED, INC.; PENGUIN SOLUTIONS CORPORATION (DE); SMART EMBEDDED COMPUTING, INC.; SMART HIGH RELIABILITY SOLUTIONS LLC; SMART MODULAR TECHNOLOGIES, INC.; PENGUIN COMPUTING, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 071755/0001 →
RELEASE OF PATENT SECURITY INTEREST RECORDED AT R/F 058983/0001 Recorded Jun 25, 2025
From: CITIZENS BANK, N.A.
To: SMART MODULAR TECHNOLOGIES, INC.; SMART EMBEDDED COMPUTING, INC.; SMART HIGH RELIABILITY SOLUTIONS LLC; CREELED, INC.
Reel/Frame 071725/0207 →
RELEASE OF SECURITY INTEREST Recorded Feb 7, 2022
From: BANK OF AMERICA, N.A., AS AGENT
To: SMART EMBEDDED COMPUTING, INC.
Reel/Frame 058913/0097 →
RELEASE OF SECURITY INTEREST AT REEL 050471 FRAME 0912 Recorded Feb 7, 2022
From: BARCLAYS BANK PLC
To: SMART EMBEDDED COMPUTING, INC.
Reel/Frame 058961/0005 →
SECURITY INTEREST Recorded Feb 7, 2022
From: SMART MODULAR TECHNOLOGIES, INC.; SMART HIGH RELIABILITY SOLUTIONS, LLC; SMART EMBEDDED COMPUTING, INC.; CREELED, INC.
To: CITIZENS BANK, N.A.
Reel/Frame 058983/0001 →
SECURITY INTEREST Recorded Dec 23, 2020
From: SMART EMBEDDED COMPUTING INC.
To: BANK OF AMERICA, N.A., AS AGENT
Reel/Frame 054739/0137 →
CHANGE OF NAME Recorded Jun 24, 2020
From: ARTESYN EMBEDDED COMPUTING, INC.
To: SMART EMBEDDED COMPUTING, INC.
Reel/Frame 053023/0953 →
SECURITY AGREEMENT Recorded Sep 24, 2019
From: SMART EMBEDDED COMPUTING, INC.
To: BARCLAYS BANK PLC
Reel/Frame 050471/0912 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2014
From: VAANANEN, PASI JUKKA PETTERI; CORNES, MARTIN PETER JOHN; PRI-TAL, SHLOMO
To: ARTESYN EMBEDDED COMPUTING, INC.
Reel/Frame 033270/0300 →