Reliable, low latency hardware and software inter-process communication channel for safety critical system
View Patent ↗A fault-tolerant failsafe computer system including an inter-processor communication channel includes a transmission control module that encodes a first data packet and communicates a first encoded copy of the first data packet and a second encoded copy of the first data packet. The system also includes a receiver control module that i) receives a first encoded copy of a second data packet and a second encoded copy of the second data packet and ii) decodes the first encoded copy and the second encoded copy. The system further includes a de-duplication module that receives a plurality of data packets and communicates at least one unique data packet of the plurality of data packets.
1. A fault-tolerant failsafe computer system including an inter-processor communication channel comprising:
a multiplexer that receives a plurality of incoming data packets from a plurality of components of the fault-tolerant failsafe computer system and selectively communicates a first data packet;
a transmission control module receiving the first data packet and encodes the first data packet and communicates a first encoded copy of the first data packet and a second encoded copy of the first data packet;
a receiver control module that i) receives a first encoded copy of a second data packet and a second encoded copy of the second data packet and ii) decodes the first encoded copy and the second encoded copy;
a de-duplication module that receives a plurality of data packets from the receiver control module and communicates at least one unique data packet of the plurality of data packets; and
a de-multiplexer that receives the at least one unique data date packet from the de-duplication module and selectively communicates the at least one unique data packet to the plurality of components of the fault-tolerant failsafe computer system.
2. The system of claim 1 further comprising a first transmitter module that receives the first encoded copy of the first data packet and a second transmitter module that receives the second encoded copy of the first data packet.
3. The system of claim 2 wherein the first transmitter module transmits the first encoded copy of the first data packet and wherein the second transmitter module transmits the second encoded copy of the first data packet.
4. The system of claim 1 further comprising a first receiver module that receives the first encoded copy of the second data packet and a second receiver module that receives the second encoded copy of the second data packet.
5. The system of claim 4 wherein the first receiver module communicates the first encoded copy of the second data packet to the receiver control module and wherein the second receiver module communicates the second encoded copy of the second data packet to the receiver control module.
6. The system of claim 1 wherein the transmission control module generates a sequence number associated with the first data packet and wherein the first data packet is encoded for error detection.
7. The system of claim 1 wherein the first encoded copy and the second encoded copy of the second data packet include a sequence number and wherein the first encoded copy and the second encoded copy of the second data packet are encoded for error detection.
8. The system of claim 7 wherein the receiver control module is configured to detect errors in the first encoded copy and the second encoded copy of the second data packet based on a predetermined protocol associated with the encoding for error detection.
9. The system of claim 7 wherein the de-duplication module receives a sequence number associated with each of the plurality of data packets and wherein the de-duplication module compares each sequence number and discards data packets associated duplicate sequence numbers.
10. A method for inter-processor communication comprising:
encoding a first data packet;
communicating a first encoded copy of the first data packet and a second encoded copy of the first data packet directly from one of a first or second computer processor to the other of the first or second computer processor;
receiving at the one of the first or second computer processor a first encoded copy of a second data packet and a second encoded copy of the second data packet from the other of the first or second computer processor;
decoding the first encoded copy and the second encoded copy of the second data packet;
receiving the first decoded copy of the second data packet and the second decoded copy of the second data packet; and
communicating at least one unique data packet of the first decoded copy of a second data packet and a second decoded copy of the second data packet.
11. The method of claim 10 further comprising receiving a plurality of incoming data packets from a plurality of components of a fault-tolerant computer system, selectively communicating the first data packet to a transmission control module, receiving the at least one unique data packet, and selectively communicating the at least one unique data packet to the plurality of components of the fault-tolerant computer system.
12. The method of claim 10 further comprising receiving the first encoded copy of the first data packet at a first transmitter module and receiving the second encoded copy of the first data packet at a second transmitter module.
13. The method of claim 12 further comprising transmitting the first encoded copy of the first data packet and transmitting the second encoded copy of the first data packet.
14. The method of claim 10 further comprising receiving the first encoded copy of the second data packet at a first receiver module and receiving the second encoded copy of the second data packet at a second receiver module.
15. The method of claim 14 further comprising communicating the first encoded copy of the second data packet to a receiver control module and communicating the second encoded copy of the second data packet to the receiver control module.
16. The method of claim 10 further comprising generating a sequence number associated with the first data packet, wherein encoding the first data packet is encoded for error detection.
17. The method of claim 10 wherein the first encoded copy and the second encoded copy of the second data packet include a sequence number and wherein the first encoded copy and the second encoded copy of the second data packet are encoded for error detection.
18. The method of claim 17 further comprising detecting errors in the first encoded copy and the second encoded copy of the second data packet based on a predetermined protocol associated with the encoding for error detection.
19. The method of claim 17 further comprising receiving a sequence number associated with each of the plurality of data packets, comparing each sequence number, and discarding data packets associated duplicate sequence numbers.
20. A fault-tolerant failsafe computer system comprising:
an inter-processor communication channel for direct communication between a first computer processor and a second computer processor, including:
a transmission control module that encodes a first data packet and communicates a first encoded copy of the first data packet and a second encoded copy of the first data packet, wherein the first encoded copy of the first data packet and the second encoded copy of the first data packet are communicated directly from one of the first computer processor or the second computer processor to the other of the first computer processor or the second computer processor;
a receiver control module that i) receives a first encoded copy of a second data packet and a second encoded copy of the second data packet from the other of the first computer processor or the second computer processor and ii) decodes the first encoded copy and the second encoded copy; and
a de-duplication module that receives a plurality of data packets from the receiver control module and communicates at least one unique data packet of the plurality of data packets.
21. The system of claim 20 further comprising a:
a multiplexer that receives a plurality of incoming data packets from a plurality of components of the fault-tolerant failsafe computer system and selectively communicates the first data packet to the transmission control module; and
a de-multiplexer that receives the at least one unique data packet from the de-duplication module and selectively communicates the at least one unique data packet to the plurality of components of the fault-tolerant failsafe computer system.
22. The system of claim 20 further comprising a first transmitter module that receives the first encoded copy of the first data packet and a second transmitter module that receives the second encoded copy of the first data packet, wherein the first transmitter module communicates the first encoded copy of the first data packet and the second transmitter module communicates second encoded copy of the first data packet from the one of the first computer processor or the second computer processor to the other of the first computer processor or the second computer processor.
23. The system of claim 20 further comprising a first receiver module that receives the first encoded copy of the second data packet from the one of the first computer processor or the second computer processor and a second receiver module that receives the second encoded copy of the second data packet from the one of the first computer processor or the second computer processor.
24. The system of claim 23 wherein the first receiver module communicates the first encoded copy of the second data packet to the receiver control module and wherein the second receiver module communicates the second encoded copy of the second data packet to the receiver control module.
25. The system of claim 20 wherein the transmission control module generates a sequence number associated with the first data packet and wherein the first data packet is encoded for error detection.
26. The system of claim 20 wherein the first encoded copy and the second encoded copy of the second data packet include a sequence number and wherein the first encoded copy and the second encoded copy of the second data packet are encoded for error detection.
27. The system of claim 26 wherein the receiver control module is configured to detect errors in the first encoded copy and the second encoded copy of the second data packet based on a predetermined protocol associated with the encoding for error detection.
28. The system of claim 26 wherein the de-duplication module receives a sequence number associated with each of the plurality of data packets and wherein the de-duplication module compares each sequence number and discards data packets associated duplicate sequence numbers.