Butted SOI junction isolation structures and devices and method of fabrication
View Patent ↗A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.
1. A structure, comprising:
a silicon layer on a buried oxide layer of a silicon-on-insulator substrate;
a first gate electrode of a field effect transistor on a top surface of a gate dielectric layer formed on a top surface of said silicon layer and a second gate of a second field effect transistor on said top surface of said gate dielectric layer;
a trench in said silicon layer between said first and second gate electrodes, said trench extending from a top surface of said silicon layer into said silicon layer, said trench not extending to said buried oxide layer;
a doped region in said silicon layer between and abutting said buried oxide layer and a bottom of said trench, said doped region doped to a first dopant concentration, said doped region and said silicon layer doped opposite dopant types;
a first epitaxial layer, doped to a second dopant concentration, in a bottom of said trench, said first epitaxial layer partially filling said trench;
a second epitaxial layer, doped to a third dopant concentration, on said first epitaxial layer in said trench; and
wherein said third dopant concentration is greater than said first and second dopant concentrations and said first dopant concentration is greater than said second dopant concentration.
2. The structure of claim 1 , wherein said doped region, said first epitaxial layer and said second epitaxial layer are all doped a same dopant type.
3. The structure of claim 1 , wherein said doped region and said second epitaxial layer are doped a first dopant type and said first epitaxial layer is doped a second and opposite dopant type.
4. The structure of claim 1 , wherein said doped region and said second epitaxial layer are doped a first dopant type and said first epitaxial layer is net doped zero or is intrinsic.
5. The structure of claim 1 , further including:
an additional doped region, doped to a fourth dopant concentration, in an upper region of said second epitaxial layer and abutting a top surface of said second epitaxial layer, said fourth dopant concentration greater than said third dopant concentration.
6. The structure of claim 5 , wherein:
(i) said doped region, said additional doped region, said first epitaxial layer and said second epitaxial layer are all doped a same dopant type; or
(ii) said doped region, said additional doped region and said second epitaxial layer are doped a first dopant type and said first epitaxial layer is doped a second and opposite dopant type; or
(iii) said doped region, said additional doped region and said second epitaxial layer are doped a first dopant type and said first epitaxial layer is net doped zero or is intrinsic.
7. The structure of claim 1 , wherein said first epitaxial layer includes silicon and excludes other group IV atoms.
8. The structure of claim 1 , wherein said first epitaxial layer includes silicon and includes germanium.
9. The structure of claim 1 , wherein said first epitaxial layer includes silicon and includes carbon.
10. The structure of claim 1 , wherein-said second epitaxial layer includes silicon and excludes other group IV atoms.
11. The structure of claim 1 , wherein said second epitaxial layer includes silicon and includes germanium.
12. The structure of claim 1 , wherein said second epitaxial layer includes silicon and includes carbon.
13. The structure of claim 1 , wherein said field effect transistor is a PFET and said second epitaxial layer does not contribute any P-type dopant species to depletion layers of a first source/drain region and a second source/drain region of said field effect transistor.
14. The structure of claim 1 , wherein said field effect transistor is an NFET and said second epitaxial layer does not contribute any N-type dopant species to depletion layers of a first source/drain region and a second source/drain region of said field effect transistor.
15. The structure of claim 1 , wherein said second epitaxial layer includes silicon and excludes other group IV atoms.
16. A field effect transistor, comprising:
a silicon layer on a buried oxide layer of a silicon-on-insulator (SOI) substrate;
first and second butted SOI junction isolations on opposite side of a channel region in said silicon layer, each butted SOI junction isolation comprising:
a trench in said silicon layer extending from a top surface of said silicon layer into said silicon layer, said trench not extending to said buried oxide layer;
a doped region in said silicon layer between and abutting said buried oxide layer and a bottom of said trench, said first doped region doped to a first dopant concentration;
a first epitaxial layer, doped to a second dopant concentration, in a bottom of said trench;
a second epitaxial layer, doped to a third dopant concentration, on said first epitaxial layer in said trench; and
wherein said third dopant concentration is greater than said first and second dopant concentrations and said first dopant concentration is greater than said second dopant concentration; and
a gate dielectric layer on a top surface of said silicon layer between said first and second butted SOI junction isolation;
a gate electrode on said gate dielectric;
wherein said doped region and said second epitaxial layers of said first and second butted SOI junction isolations are all doped a same dopant type and a body region of said silicon layer between said first and second butted junction SOI isolation is doped a second and opposite dopant type.
17. The field effect transistor of claim 16 , wherein said first epitaxial layers of said first and second butted SOI junction isolations are doped said first dopant type.
18. The field effect transistor of claim 16 , wherein said first epitaxial layers of said first and second butted SOI junction isolations are doped said second type.
19. The field effect transistor of claim 16 , wherein said second epitaxial layers of said first and second butted SOI junction isolations are net doped zero or is intrinsic.
20. The field effect transistor of claim 16 , further including:
a first source/drain extension under said gate electrode, and abutting said first epitaxial layer of said first butted SOI junction isolation;
a second source/drain extension under said gate electrode and abutting said second epitaxial layer of said first butted SOI junction isolation; and
wherein said first and second source/drain extension are doped said first dopant type.
21. The field effect transistor of claim 16 , further including:
a first source/drain region in said second epitaxial layer of said first butted SOI junction isolation, said first source/drain doped to a fourth dopant concentration and abutting a top surface of said second epitaxial layer, said fourth dopant concentration greater than said third dopant concentration;
a second source/drain region in said second epitaxial layer of said second butted SOI junction isolation, said second source/drain doped to said fourth dopant concentration and abutting a top surface of said second epitaxial layer; and
wherein said fourth dopant concentration is greater than said third dopant concentration.
22. The field effect transistor of claim 21 , further including:
a first source/drain extension under said gate electrode, and abutting said first source/drain;
a second source/drain extension under said gate electrode and abutting said second source/drain; and
wherein said first and second source/drain extension are doped said first dopant type.
23. The field effect transistor of claim 21 , wherein said field effect transistor is a PFET and said second epitaxial layer does not contribute any P-type dopant species to depletion layers of said first source/drain region and said second source/drain region.
24. The field effect transistor of claim 21 , wherein said field effect transistor is an NFET and said second epitaxial layer does not contribute any N-type dopant species to depletion layers of said first source/drain region and said second source/drain region.
25. The field effect transistor of claim 16 , wherein said first epitaxial layers of said first and second butted SOI junction isolations and said second epitaxial layers of said first and second butted SOI junction isolations each independently include silicon and (i) exclude other group IV atoms, or (ii) include germanium, or (iii) include carbon.
26. The field effect transistor of claim 16 , wherein said first epitaxial layer includes silicon and includes germanium.
27. The field effect transistor of claim 16 , wherein said first epitaxial layer includes silicon and includes carbon.
28. The field effect transistor of claim 16 , wherein-said second epitaxial layer includes silicon and excludes other group IV atoms.
29. The field effect transistor of claim 16 , wherein said second epitaxial layer includes silicon and includes germanium.
30. The field effect transistor of claim 16 , wherein said second epitaxial layer includes silicon and includes carbon.