Method of forming semiconductor fins
Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.
1. A method of forming a semiconductor structure, comprising:
depositing a high-K dielectric layer on a semiconductor substrate;
forming a plurality of fin hardmask regions disposed on the high-K dielectric layer;
depositing a lithography stack on the semiconductor structure;
performing a first etch into the lithography stack to expose a portion of at least one fin hardmask region, the hardmask region being comprised of a first hardmask portion disposed on a second hardmask portion, wherein a subset of fin hardmask regions remain covered by the lithography stack;
performing a second etch to remove the first hardmask portion of the exposed hardmask region;
removing the lithography stack;
performing a third etch to remove the second hardmask portion of the exposed hardmask region;
performing a substrate recess to form fins at locations of the subset of fin hardmask regions; and
removing the subset of fin hardmask regions.
2. The method according to claim 1 , wherein the depositing a high-K dielectric layer comprises depositing aluminum oxide.
3. The method according to claim 1 , wherein the depositing a high-K dielectric layer comprises depositing hafnium oxide.
4. The method according to claim 1 , wherein the depositing a lithography stack comprises:
depositing a carbon layer on the high-K dielectric layer and fin hardmask regions;
depositing a nitride layer on the carbon layer; and
depositing a photoresist layer on the nitride layer.
5. The method according to claim 1 , wherein the performing a first etch into the lithography stack to expose a portion of at least one fin hardmask region comprises performing a reactive ion etch.
6. The method according to claim 1 , wherein the performing a second etch to remove the first hardmask portion of the exposed hardmask region comprises performing an isotropic etch.
7. The method according to claim 1 , wherein the performing a third etch to remove the second hardmask portion of the exposed hardmask region comprises performing an anisotropic etch.
8. A method of forming a semiconductor structure, comprising:
depositing an aluminum oxide dielectric layer on a semiconductor substrate;
forming a plurality of fin hardmask regions disposed on the aluminum oxide dielectric layer;
depositing a lithography stack on the semiconductor structure;
performing a first etch into the lithography stack to expose a portion of at least one fin hardmask region, the hardmask region being comprised of a silicon nitride portion disposed on a silicon oxide portion, wherein a subset of fin hardmask regions remain covered by the lithography stack;
performing a second etch to remove the silicon nitride portion of the exposed hardmask region;
removing the lithography stack;
performing a third etch to remove the silicon oxide portion of the exposed hardmask region;
performing a substrate recess to form fins at locations of the subset of fin hardmask regions; and
removing the subset of fin hardmask regions.
9. The method according to claim 8 , wherein the depositing a lithography stack comprises:
depositing a carbon layer on the aluminum oxide dielectric and fin hardmask regions;
depositing a nitride layer on the carbon layer; and
depositing a photoresist layer on the nitride layer.
10. The method according to claim 8 , wherein the performing a first etch into the lithography stack to expose a portion of at least one fin hardmask region comprises performing a reactive ion etch.
11. The method according to claim 8 , wherein the performing a second etch comprises performing an isotropic etch selective to silicon nitride.
12. The method according to claim 8 , wherein the performing a third etch comprises performing an anisotropic etch.
13. The method according to claim 8 , further comprising removing the aluminum oxide layer after the step of performing a third etch to remove the silicon oxide portion of the exposed hardmask region.
14. The method according to claim 8 , wherein the removing the aluminum oxide layer is performed using a chlorine-based etch process.
15. A method of forming a semiconductor structure, comprising:
depositing a high-K dielectric layer on a semiconductor substrate;
forming a plurality of fin hardmask regions disposed on the high-K dielectric layer;
depositing a lithography stack on the semiconductor structure;
performing a first etch into the lithography stack to expose only a portion of at least one fin hardmask region, the hardmask region being comprised of a silicon nitride portion disposed on a silicon oxide portion, wherein a subset of fin hardmask regions remain covered by the lithography stack;
performing a second etch to remove the silicon nitride portion of the exposed hardmask region;
removing the lithography stack;
performing a third etch to remove the silicon oxide portion of the exposed hardmask region;
performing a substrate recess to form fins at locations of the subset of fin hardmask regions;
depositing a gap fill dielectric layer over the fins; and
recessing the gap fill dielectric layer to a level below a top of the fins.
16. The method according to claim 15 , wherein the depositing a high-K dielectric layer comprises depositing aluminum oxide.
17. The method according to claim 15 , wherein the depositing a high-K dielectric layer comprises depositing hafnium oxide.
18. The method according to claim 15 , wherein the depositing a lithography stack comprises:
depositing a carbon layer on the high-K dielectric layer and fin hardmask regions;
depositing a nitride layer on the carbon layer; and
depositing a photoresist layer on the nitride layer.
19. The method according to claim 15 , wherein the performing a first etch into the lithography stack to expose a portion of at least one fin hardmask region comprises performing a reactive ion etch.
20. The method according to claim 15 , wherein the performing a second etch to remove the silicon nitride portion of the exposed hardmask region comprises performing an isotropic etch.