Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory
View Patent ↗In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel boosting. To provide a sufficient but not excessive level of boosting, the amount of boosting can be set based on a data state of the unselected storage element. A greater amount of boosting can be provided for a lower data state which represents a lower threshold voltage and hence is more vulnerable to program disturb. A common boosting scheme can be used for groups of multiple data states. The amount of boosting can be set by adjusting the timing and magnitude of voltages used for a channel pre-charge operation and for pass voltages which are applied to word lines. In one approach, stepped pass voltages on unselected word lines can be used to adjust boosting for channels with selected data states.
1. A method for operating a non-volatile storage system, comprising:
performing at least one programming iteration in which a program pulse is applied to a selected word line, the selected word line is in communication with a subset of storage elements in a set of storage elements which is formed on a substrate, and the selected word line is one word line of a plurality of word lines which are in communication with the set of storage elements; and
prior to applying the program pulse, determining that a first unselected storage element in the subset of storage elements has a data state which is in a first group of one or more data states, determining that a second unselected storage element in the subset of storage elements has a data state which is in a second group of one or more data states, boosting a first channel region of the substrate which is associated with the first unselected storage element using a first boosting scheme associated with the first group, and boosting a second channel region of the substrate which is associated with the second unselected storage element using a second boosting scheme associated with the second group.
2. The method of claim 1 , wherein:
the first and second unselected storage elements are storage elements which are locked out from programming.
3. The method of claim 1 , wherein:
at least one of the first and second groups is associated with multiple data states.
4. The method of claim 1 , wherein:
the first group is associated with one or more verify levels which are lower than one or more verify levels with which the second group is associated; and
the first boosting scheme boosts the first channel region to a higher level than a level to which the second channel region is boosted by the second boosting scheme.
5. The method of claim 1 , wherein:
the first and second storage elements are in communication with first and second bit lines, respectively;
the first boosting scheme involves boosting the first channel region via the first bit line, and subsequently boosting the first channel region further via pass voltages which are applied to the plurality of word lines; and
the second boosting scheme precludes boosting of the second channel region via the second bit line, and subsequently boosts the second channel region via the pass voltages which are applied to the plurality of word lines.
6. The method of claim 1 , wherein:
the first and second storage elements are in communication with first and second bit lines, respectively;
the first boosting scheme involves boosting the first channel region via the first bit line, and subsequently boosting the first channel region further via pass voltages which are applied to the plurality of word lines; and
the second boosting scheme involves boosting the second channel region via the second bit line, the second channel region is boosted via the second bit line to a lesser extent than an extent to which the first channel is boosted via the first bit line, and subsequently boosting the second channel region further via the pass voltages which are applied to the plurality of word lines.
7. The method of claim 1 , wherein:
the first storage element is in communication with a dummy drain-side storage element and a bit line; and
the first boosting scheme involves boosting the first channel region via the first bit line, by controlling the dummy drain-side storage element to be in a conductive state and to subsequently be in a non-conductive state, and subsequently boosting the first channel region further via pass voltages which are applied to the plurality of word lines.
8. The method of claim 1 , wherein:
the first and second storage elements are in communication with first and second bit lines, respectively; and
the first and second boosting schemes involve boosting the first and second channel regions, respectively, via pass voltages which are applied to the plurality of word lines, the pass voltages are applied in multiple steps, a voltage of the first bit line is raised before the pass voltages are applied, and a voltage of the second bit line is raised during one step of the multiple steps, prior to a last step of the multiple steps.
9. The method of claim 1 , wherein:
the determining that the first unselected storage element has a data state which is in the first group comprises accessing at least one latch which is associated with the first unselected storage element.
10. The method of claim 9 , wherein:
the at least one latch was used in a previous programming iteration to indicate that the first unselected storage element was subject to slow speed programming.
11. The method of claim 1 , wherein:
the boosting of the first and second channel regions provides the first and second channels at respective first and second boosted levels when the program pulse is applied.
12. A non-volatile storage system, comprising:
a set of non-volatile storage elements formed on a substrate, a subset of storage elements in the set of storage elements includes first and second unselected storage elements, and the substrate includes first and second channels regions which are associated with the first and second unselected storage elements, respectively;
a set of word lines in communication with the set of non-volatile storage elements, including a selected word line which is in communication with the subset of storage elements, where the selected word line is one word line of a plurality of word lines which are in communication with the set of storage elements; and
at least one control circuit, the at least one control circuit: (a) performs at least one programming iteration in which a program pulse is applied to the selected word line, and (b) prior to when the program pulse is applied, determines that the first unselected storage element has a data state which is in a first group of one or more data states, determines that the second unselected storage element has a data state which is in a second group of one or more data states, boosts a first channel region of the substrate which is associated with the first unselected storage element using a first boosting scheme associated with the first group, and boosts a second channel region of the substrate which is associated with the second unselected storage element using a second boosting scheme associated with the second group.
13. The non-volatile storage system of claim 12 , wherein:
at least one of the first and second groups is associated with multiple data states.
14. The non-volatile storage system of claim 12 , wherein:
the first group is associated with one or more verify levels which are lower than one or more verify levels with which the second group is associated; and
the first boosting scheme boosts the first channel region to a higher level than a level to which the second channel region is boosted by the second boosting scheme.
15. The non-volatile storage system of claim 12 , wherein:
the first and second storage elements are in communication with first and second bit lines, respectively;
in the first boosting scheme, the at least one control circuit boosts the first channel region via the first bit line, and subsequently boosts the first channel region further via pass voltages which are applied to the plurality of word lines; and
in the second boosting scheme, at least one control circuit precludes boosting of the second channel region via the second bit line, and subsequently boosts the second channel region via the pass voltages which are applied to the plurality of word lines.
16. The non-volatile storage system of claim 12 , wherein:
the first and second storage elements are in communication with first and second bit lines, respectively;
in the first boosting scheme, at least one control circuit boosts the first channel region via the first bit line, and subsequently boosts the first channel region further via pass voltages which are applied to the plurality of word lines; and
in the second boosting scheme, at least one control circuit boosts the second channel region via the second bit line, where the second channel region is boosted via the second bit line to a lesser extent than an extent to which the first channel is boosted via the first bit line, and subsequently boosts the second channel region further via the pass voltages which are applied to the plurality of word lines.
17. The non-volatile storage system of claim 12 , wherein:
the first storage element is in communication with a dummy drain-side storage element and a bit line; and
in the first boosting scheme, at least one control circuit boosts the first channel region via the first bit line, by controlling the dummy drain-side storage element to be in a conductive state and subsequently be in a non-conductive state, and subsequently boosts the first channel region further via pass voltages which are applied to the plurality of word lines.
18. The non-volatile storage system of claim 12 , wherein:
the first and second storage elements are in communication with first and second bit lines, respectively; and
in the first and second boosting schemes, at least one control circuit boosts the first and second channel regions, respectively, via pass voltages which are applied to the plurality of word lines, the pass voltages are applied in multiple steps, a voltage of the first bit line is raised before the pass voltages are applied, and a voltage of the second bit line is raised during one step of the multiple steps, prior to a last step of the multiple steps.
19. The method of claim 1, wherein:
the set of storage elements is arranged in a three-dimensional memory structure.
20. The non-volatile storage system of claim 12, wherein:
the set of non-volatile storage elements is arranged in a three-dimensional memory structure.