Circuits having programmable impedance elements and vertical access devices
View Patent ↗A memory device can include at least one programmable impedance cell having at least one programmable layer formed between a first terminal and a second terminal, the programmable layer being programmable between at least two impedance states by application of electric fields; and at least a first access bipolar junction transistor (BJT) coupled to the programmable impedance cell having at least a portion formed by a semiconductor material; wherein a base region and a first emitter region or collector region of the first access BJT are vertically aligned with one another.
1. A memory device, comprising:
at least one programmable impedance cell having at least one programmable layer formed between a first terminal and a second terminal, the programmable layer being programmable between at least two impedance states by application of electric fields; and
at least a first access bipolar junction transistor (BJT) coupled to the programmable impedance cell having at least a portion formed by a semiconductor material; wherein
a base region and a first emitter region or collector region of the first access BJT are vertically aligned with one another.
2. The memory device of claim 1 , wherein:
the programmable impedance cell comprises an ion conductor material disposed between a first and second electrode.
3. The memory device of claim 1 , wherein:
the base region is formed in a portion of a first semiconductor film; and
the first emitter or collector region is formed in the portion of the first semiconductor film; wherein
the first semiconductor film is formed on an insulating layer formed over a substrate.
4. The memory device of claim 3 , wherein:
the first semiconductor film includes silicon.
5. The memory device of claim 3 , wherein:
the at least one first access BJT includes a second emitter or collector region formed in a portion of a second semiconductor film disposed below the first semiconductor film.
6. The memory device of claim 5 , wherein:
the portion of the first semiconductor film comprises a first patterned line; and
the portion of the second semiconductor film comprises a second patterned line.
7. The memory device of claim 3 , wherein
the at least one first access BJT includes a second emitter or collector region formed in a portion of a substantially monocrystalline substrate.
8. The memory device of claim 3 , wherein:
the first semiconductor film includes
a first area comprising a first region doped to a first conductivity type forming at least a portion of a common base for a plurality of first access BJTs, and
a plurality of second regions doped to a second conductivity type, each second region forming at least a portion of first emitter or collector region of access BJTs, only one of which is included in the first access BJTs.
9. The memory device of claim 1 , further including:
at least a second programmable impedance cell having a first terminal and a second terminal and formed over the first programmable impedance cell; and
at least one second access BJT coupled to the second programmable impedance cell, the second access BJT having at least a portion formed by at least one semiconductor film formed over a substrate, the at least one second access BJT being formed over the first access BJT.