IP Library Granted Patent US 9,165,356
Granted Patent B2
US 9,165,356 · App. 14/238,105 · Granted Oct 20, 2015

Defect inspection method and defect inspection device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,165,356
App. No.
14/238,105
Granted
Oct 20, 2015
Kind
B2
Abstract

A defect inspection method for inspecting a defect on a semiconductor wafer, using plural inspection methods includes: merging hot-spot coordinates as coordinates on the semiconductor wafer, designated by a user, or coordinates where a systematic defect can occur, with detected defect coordinates on the semiconductor wafer, acquired from inspection information, after information indicating the type of coordinates are added thereto; deciding an inspection sequence of the coordinates merged with each other; and defect inspection for executing selection using the information indicating the respective types of the coordinates merged with each other, and executing an inspection by selecting an inspection method for every coordinates to be inspected.

Claims (33)

1. A method for inspecting a semiconductor, comprising:

merging first coordinates and second coordinates of locations on the semiconductor, wherein the first coordinates and the second coordinates have respective coordinate type information, the first coordinates are hot-spot coordinates where a systematic defect can occur, and the second coordinates are defect coordinates of the semiconductor;

deciding an inspection sequence of the merged coordinates; and

inspecting the merged coordinates using a selected inspection method that is selected from a plurality of different inspection methods based on the respective coordinate type information.

2. The method according to claim 1 ,

wherein the inspection sequence is decided based on moving time of a stage located under the semiconductor.

3. The method according to claim 1 ,

wherein the different inspection methods are a first inspection method to inspect the first coordinates and a second inspection method to inspect the second coordinates.

4. The method according to claim 1 , further comprising obtaining a coincidence value of a first image of the first coordinates and a second image of the second coordinates.

5. The method according to claim 4 further comprising comparing the coincidence value and a predetermined value.

6. The method according to claim 5 , further comprising changing type information of the second coordinates to type information of the first coordinates based on a result of the comparing the coincidence value and the predetermined value.

7. The method according to claim 4 ,

wherein type information of the first coordinates is systematic defect, and

wherein the second coordinates are obtained in advance by another inspection system.

8. The method according to claim 4 , wherein the second coordinates are picked up as candidates of the hot-spot coordinates in case the coincidence value is high.

9. The method according to claim 1 , further comprising steps of capturing a reference image, capturing a defect image of the second coordinates, detecting a defect site by comparing the reference image and the defect image, and capturing an observation image.

10. The method according to claim 1 , further comprising steps of capturing an image of a hot-spot in the semiconductor, detecting a defect, and classifying the defect.

11. A device for inspecting a semiconductor, comprising:

an operation unit that merges first coordinates and second coordinates of locations on the semiconductor, wherein the first coordinates and the second coordinates have respective coordinate type information, the first coordinates are hot-spot coordinates where a systematic defect can occur, and the second coordinates are defect coordinates of the semiconductor, and decides an inspection sequence of the merged coordinates; and

a control unit that inspects the merged coordinates using a selected inspection method that is selected from a plurality of different inspection methods based on the respective coordinate type information.

12. The device according to claim 11 ,

wherein the inspection sequence is decided based on moving time of a stage located under the semiconductor.

13. The device according to claim 11 ,

wherein the different inspection methods are a first inspection method to inspect the first coordinates and a second inspection method to inspect the second coordinates.

14. The device according to claim 11 , wherein the operation unit obtains a coincidence value of a first image of the first coordinates and a second image of the second coordinates.

15. The device according to claim 14 , wherein the operation unit compares the coincidence value and a predetermined value.

16. The device according to claim 15 , wherein the operation unit changes type information of the second coordinates to type information of the first coordinates based on a result of the comparing the coincidence value and the predetermined value.

17. The device according to claim 14 ,

wherein type information of the first coordinates is a systematic defect, and

wherein the second coordinates are obtained in advance by another inspection system.

18. The device according to claim 14 , wherein the second coordinates are picked up as candidates of the hot-spot coordinates in case the coincidence value is high.

19. The device according to claim 11 , wherein the operation unit captures a reference image, captures a defect image of the second coordinates, detects a defect site by comparing the reference image and the defect image, and captures an observation image.

20. The device according to claim 11 , wherein the operation unit captures an image of a hot-spot in the semiconductor, detects a defect, and classifies the defect.

Assignments (2)
CHANGE OF NAME AND ADDRESS Recorded Mar 30, 2020
From: HITACHI HIGH-TECHNOLOGIES CORPORATION
To: HITACHI HIGH-TECH CORPORATION
Reel/Frame 052259/0227 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2014
From: HARADA, MINORU; MIYAMOTO, ATSUSHI; HIRAI, TAKEHIRO; FUKUNAGA, FUMIHIKO
To: HITACHI HIGH-TECHNOLOGIES CORPORATION
Reel/Frame 032196/0346 →