Apparatuses and methods of reading memory cells based on response to a test pulse
The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. The method additionally comprises determining whether a threshold voltage (Vth) of the memory cell has a value within a predetermined read voltage window. A test pulse is applied to the memory cell if it is determined that the threshold voltage has a value within the predetermined read voltage window. The state of the memory cell may be determined based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the pluralities of states of the memory cell prior to receiving the test pulse.
1. A method of reading a memory cell in a memory array including a plurality of memory cells, the method comprising:
providing the plurality of memory cells in a plurality of different states;
determining whether a threshold voltage (Vth) of a memory cell of the plurality of memory cells has a value within a predetermined read voltage window in which threshold voltages of at least some of the memory cells in different states overlap;
applying a test pulse to the memory cell having the threshold voltage within the predetermined read voltage window; and
determining the state of the memory cell based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the plurality of states of the memory cell prior to receiving the test pulse.
2. The method of claim 1 , wherein applying the test pulse changes a state of the memory cell and further comprising, after determining the state of the memory cell, refreshing the memory cell to the state of the memory cell prior to receiving the test pulse.
3. The method of claim 1 , wherein applying the test pulse comprises thresholding the memory cell such that a snap-back discharge current flows through the memory cell.
4. The method of claim 1 , wherein the memory cell comprises a phase change memory cell having at least one of a storage node or a selector node comprising a chalcogenide material.
5. The method of claim 4 , wherein one of the plurality of states corresponds to a SET state and the other of the plurality of states corresponds to a RESET state.
6. The method of claim 5 , wherein applying the test pulse comprises applying one of a READ pulse or a SET pulse.
7. The method of claim 6 , wherein the memory cell prior to receiving the test pulse is in a RESET state, and wherein applying the test pulse comprises applying a bit-altering test pulse such that the state of the memory cell is changed to a SET state.
8. The method of claim 7 , wherein determining the state of the memory cell comprises determining that the state of the memory cell was a RESET state prior to receiving the test pulse based on a determination that the state of the memory cell is in a SET state after applying the test pulse.
9. The method of claim 5 , wherein applying the test pulse comprises applying a RESET pulse.
10. The method of claim 9 , wherein the memory cell prior to receiving the test pulse is in a SET state, and wherein applying the test pulse comprises applying a bit-altering test pulse such that the state of the memory cell is changed to a RESET state.
11. The method of claim 10 , wherein determining the state of the memory cell comprises determining that the state of the memory cell was a SET state prior to receiving the test pulse based on a determination that the state of the memory cell is in a RESET state after applying the test pulse.
12. The method of claim 1 , wherein providing the memory array comprises providing a plurality of memory cells, further comprising:
applying at least one of a SET pulse or a RESET pulse to each memory cell of the memory array such that the memory array has a SET distribution comprising memory cells that have received SET pulses and has a RESET distribution comprising memory cells that have received RESET pulses.
13. The method of claim 12 , wherein a lowest Vth of the RESET distribution has a Vth value lower than a highest Vth of the SET distribution such that the predetermined read voltage window has a negative value.
14. The method of claim 1 , wherein upon determining that the threshold voltage (Vth) of the memory cell has a value within the predetermined read voltage window, applying an error correction code instead of or in addition to proceeding to apply the test pulse.
15. An apparatus comprising:
an array of a plurality of memory cells in a plurality of different states; and
a memory controller configured to:
determine whether a threshold voltage (Vth) of a memory cell of the plurality of memory cells has a value within a predetermined read voltage window in which threshold voltages of at least some of the memory cells in different states overlap;
cause a test pulse to be applied to the memory cell upon determining that the threshold voltage has a value within the predetermined read voltage window; and
determine the state of the memory cell prior to receiving the test pulse based on a response of the memory cell to the test pulse.
16. The apparatus of claim 15 , wherein the memory controller is further configured to, after determining the state of the memory cell, refresh the memory cell to the state prior to receiving the test pulse.
17. The apparatus of claim 15 , wherein causing the test pulse to be applied comprises causing the memory cell to be thresholded such that a snap-back discharge current flows through the memory cell.
18. The apparatus of claim 15 , wherein the memory cell comprises a phase change memory cell having at least one of a storage node or a selector node comprising a chalcogenide material.
19. The memory cell of claim 18 , wherein one of the first and second states corresponds to a SET state and the other of the first and second states corresponds to a RESET state.
20. The apparatus of claim 15 , wherein causing the test pulse to be applied comprises causing one of a bit-altering READ pulse or a bit-altering SET pulse to be applied.
21. The apparatus of claim 20 , wherein the memory controller is configured to determine that the state of the memory cell was a RESET state prior to receiving the test pulse based on a determination that the state of the memory cell is in a SET state after applying the test pulse.
22. The apparatus of claim 21 , wherein the memory controller is configured to determine that the state of the memory cell was a SET state prior to receiving the test pulse based on a determination that the state of the memory cell is in a RESET state after applying the test pulse.
23. The apparatus of claim 15 , wherein the memory array comprises a cross point array, wherein the memory cell is disposed at an intersection between a column and a row.