Input match network with RF bypass path
View Patent ↗A power circuit includes a RF transistor and an input match network coupled to an input to the RF transistor and to an input to the power circuit. The input match network includes a resistor, an inductor and a first capacitor coupled together in series between the input to the RF transistor and a ground, and a second capacitor coupled in parallel with at least the resistor. The value of the second capacitor is selected so that the resistor is bypassed over at least a portion of the high frequency range of the power circuit.
1. A power circuit, comprising:
an RF transistor;
an input match network coupled to an input to the RF transistor and to an input to the power circuit, the input match network including a resistor, an inductor and a first capacitor coupled together in series between the input to the RF transistor and a ground, and a second capacitor coupled in parallel with at least the resistor,
wherein the values of the resistor and the inductor are selected to match an input impedance of the RF transistor to a source impedance at the input of the power circuit over at least a portion of a high frequency range,
wherein the value of the first capacitor is selected so that the series combination of the resistor, the inductor and the first capacitor reduce the magnitude of the impedance presented to the input of the RF transistor in a low frequency range relative to the source impedance at the input of the power circuit,
wherein the value of the second capacitor is selected so that the resistor is bypassed over at least a portion of the high frequency range.
2. The power circuit of claim 1 , wherein the low frequency range is from about 0 to about 300 MHz.
3. The power circuit of claim 1 , wherein the high frequency range is from about 400 MHz to about 4 GHz.
4. The power circuit of claim 1 , further comprising:
an output match network coupled to an output of the RF transistor and to an output to the power circuit,
wherein a difference between a gain response peak in the baseband range and a gain response at an intended RF operating frequency for the power circuit is equal to or greater than 28 dB.
5. The power circuit of claim 1 , wherein a ratio of the magnitude of the impedance presented to the input of the RF transistor to the source impedance at the input of the power circuit over a 1 to 300 MHz frequency range is equal to or less than 0.4.
6. The power circuit of claim 1 , wherein a ratio of the magnitude of the impedance presented to the input of the RF transistor to the source impedance at the input of the power circuit over a 1 to 300 MHz frequency range is between about 0.02 and about 0.4.
7. The power circuit of claim 1 , wherein the magnitude of the impedance presented to the input of the RF transistor is equal to or less than 20 ohms for frequencies ranging from 1 MHz up to at least one-third of an intended RF operating frequency.
8. The power circuit of claim 1 , wherein the RF transistor is a MOS transistor.
9. The power circuit of claim 1 , wherein the RF transistor is a LDMOS transistor.
10. The power circuit of claim 1 , wherein the RF transistor is a GaN MESFET transistor.
11. The power circuit of claim 1 , wherein the value of the first capacitor is in the nF range and the value of the second capacitor is in the pF range.
12. The power circuit of claim 1 , wherein the second capacitor is coupled in parallel with only the resistor.
13. The power circuit of claim 1 , wherein the second capacitor is coupled in parallel with the resistor and the first capacitor.
14. An RF power amplifier, comprising:
an input configured to receive a RF signal having a RF signal bandwidth;
a LDMOS transistor configured to amplify the RF signal;
an input match network coupled to the input of the RF power amplifier and a gate of the LDMOS transistor, the input match network including a resistor, an inductor and a first capacitor coupled together in series between the input of the RF power amplifier and a ground, and a second capacitor coupled in parallel with at least the resistor,
wherein the values of the resistor and the inductor are selected to match an impedance at the gate of the LDMOS transistor to a source impedance at the input of the RF power amplifier over at least a portion of the RF signal bandwidth,
wherein the value of the first capacitor is selected so that the input match network substantially reduces the magnitude of the impedance presented to the gate of the LDMOS transistor in a baseband frequency range relative to the source impedance at the input of the RF power amplifier,
wherein the value of the second capacitor is selected so that the resistor is bypassed over at least a portion of the RF signal bandwidth.
15. The RF power amplifier of claim 14 , wherein the baseband frequency range is from about 0 to about 300 MHz.
16. The RF power amplifier of claim 14 , wherein the RF signal bandwidth is from about 400 MHz to about 4 GHz.
17. The RF power amplifier of claim 14 , wherein the value of the first capacitor is in the nF range and the value of the second capacitor is in the pF range.
18. The RF power amplifier of claim 14 , wherein the second capacitor is coupled in parallel with only the resistor.
19. The RF power amplifier of claim 14 , wherein the second capacitor is coupled in parallel with the resistor and the first capacitor.
20. A power circuit, comprising:
an RF transistor;
an input match network coupled to an input to the RF transistor and to an input to the power circuit, the input match network including a resistor, an inductor and a first capacitor coupled together in series between the input to the RF transistor and a ground, and a second capacitor coupled in parallel with at least the resistor,
wherein the value of the resistor is in the milliohm range, the value of the inductor is in the pH range, the value of the first capacitor is in the nF range, and the value of the second capacitor is in the pF range.