Low-noise low-distortion signal acquisition circuit and method with reduced area utilization
View Patent ↗A sample and hold amplifier includes an input node for receiving an input current signal, a non-linear sampling capacitor circuit having an input coupled to the input node, an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal, and a linear capacitor coupled between the negative input and the output of the operational amplifier. The non-linear sampling capacitor includes a non-linear capacitor coupled between an intermediate node and ground, a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal, and a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal.
1. A sample and hold amplifier comprising:
an operational amplifier having a negative input, a positive input coupled to ground, and an output;
a non-linear capacitor having a first terminal, and a second terminal coupled to the negative input of the operational amplifier;
a linear capacitor having a first terminal, and a second terminal coupled to the negative input of the operational amplifier;
a first switch coupled between the first terminal of the non-linear capacitor and the output of the operational amplifier;
a second switch coupled between the first terminal of the non-linear capacitor and ground;
a third switch coupled between an input node and the negative input of the operational amplifier;
a fourth switch coupled between a first terminal of the linear capacitor and ground; and
a fifth switch coupled between a first terminal of the linear capacitor and the output of the operational amplifier.
2. The sample and hold amplifier according to claim 1 wherein the first switch is configured to switch according to a first phase signal.
3. The sample and hold amplifier according to claim 2 wherein the third and fourth switches are configured to switch according to the first phase signal.
4. The sample and hold amplifier according to claim 1 wherein the second switch is configured to switch according to a second phase signal.
5. The sample and hold amplifier according to claim 1 wherein the fifth switch is configured to switch according to the second phase signal.
6. The sample and hold amplifier according to claim 1 wherein the input node receives an input current signal.
7. The sample and hold amplifier according to claim 6 wherein the input current signal is provided by a photodiode.
8. The sample and hold amplifier according to claim 1 further comprising a reset switch coupled between the negative input of the operational amplifier and the output of the operational amplifier.
9. The sample and hold amplifier according to claim 8 wherein the reset switch is configured for receiving a reset signal.
10. The sample and hold amplifier according to claim 1 further comprising a load capacitor coupled to the output of the operational amplifier.
11. The sample and hold amplifier according to claim 10 wherein the load capacitor comprises a linear capacitor.
12. The sample and hold amplifier according to claim 10 wherein the load capacitor is coupled to the output of the operational amplifier through a load switch.
13. The sample and hold amplifier according to claim 12 wherein at least the first switch is configured to switch according to a first phase signal and the load switch is configured to switch according to a second phase signal.
14. The sample and hold amplifier according to claim 12 wherein at least one of the third or fourth switches is configured to switch according to a first phase signal and the load switch is configured to switch according to a second phase signal.