Profile of through via protrusion in 3DIC interconnect

1. A method of forming an interconnect structure, the method comprising:

forming a through via in a substrate, the through via isolated from the substrate by a liner, the liner interposed between the through via and the substrate;

performing a chemical mechanical polishing (CMP) process to selectively planarize a backside surface of the substrate, the CMP process generating a tapered profile portion of the substrate protruding above a horizontal backside surface, the tapered profile portion adjacent to the liner;

forming a dielectric capping layer over the tapered profile portion of the substrate and a backside surface of the through via, wherein a first height measured from the horizontal backside surface of the substrate to an uppermost surface of the tapered profile portion is greater than a second height measured from the uppermost surface of the tapered profile portion to an uppermost extent of the dielectric capping layer; and

planarizing the dielectric capping layer, the liner, and the through via such that a backside uppermost surface of the dielectric capping layer and a backside uppermost surface of the liner are at a substantially same level, wherein after the planarizing, a first width measured from a sidewall of the liner to the outermost extent of the planarized backside uppermost surface of the dielectric capping layer is greater than a second width measured from the sidewall of the liner to the outermost extent of the tapered profile portion.

2. The method of claim 1 , wherein the forming the dielectric capping layer comprises planarizing the dielectric capping layer to expose the backside surface of the through via.

3. The method of claim 1 , further comprising forming a redistribution layer over the through via such that the redistribution layer is electrically coupled to the through via.

4. The method of claim 1 , wherein the selectively planarizing the backside surface of the substrate forms an angle between a sidewall of the liner and an exterior surface of the tapered profile portion greater than or equal to about thirty degrees.

5. The method of claim 1 , wherein the first height is greater than or equal to about forty percent of a third height of the liner measured from the horizontal backside surface of the substrate to the backside uppermost surface of the liner.

6. The method of claim 2 , wherein the dielectric capping layer extends along a sidewall of the liner.

7. The method of claim 1 , wherein the backside uppermost surface of the liner is free of the dielectric capping layer.

8. A method of forming an interconnect structure, the method comprising:

forming a through via in a substrate, the through via comprising a liner;

performing a chemical mechanical polishing (CMP) process to selectively planarize a surface of the substrate, the CMP process exposing the through via and producing a recessed surface of the substrate such that the through via protrudes from the recessed surface of the substrate, a portion of the recessed surface of the substrate sloping toward a protruding end of the through via;

forming a dielectric capping layer over the surface of the substrate adjacent the through via, wherein a backside surface of the dielectric capping layer and a backside surface of the through via are at a substantially same level; and

forming a redistribution layer over the through via such that the redistribution layer is electrically coupled to the through via, wherein, after forming the redistribution layer, a first vertical distance between a level of the substrate laterally adjacent a substantially planar recessed surface of the substrate and an uppermost extent of material of the substrate is greater than a second vertical distance between the uppermost extent of material of the substrate and an uppermost extent of the dielectric capping layer, wherein an uppermost surface of the dielectric capping layer and an uppermost surface of the liner are at a substantially same level, wherein a first horizontal distance between a sidewall of the through via and the substantially planar recessed surface of the substrate is less than a second horizontal distance between the sidewall of the through via and the outermost extent of the uppermost surface of the dielectric capping layer.

9. The method of claim 8 , wherein forming the through via comprises:

forming an opening in the substrate;

forming the liner in the opening of the substrate; and

forming a conductive material over the liner in the opening, thereby forming the through via.

10. The method of claim 9 , wherein the liner protrudes from the surface of the substrate.

11. The method of claim 9 , wherein the forming the dielectric capping layer comprises:

forming a dielectric layer over the surface of the substrate, the through via, and the liner; and

planarizing the dielectric layer to expose the through via, thereby forming the dielectric capping layer.

12. The method of claim 11 , wherein planarizing the dielectric layer exposes the liner.

13. The method of claim 8 , wherein a first portion of the redistribution layer is above a top surface of the through via, and a second portion of the redistribution layer is below the top surface of the through via.

14. The method of claim 8 , wherein after the selectively planarizing the surface of the substrate slopes toward the protruding end of the through via at an angle less than or equal to 60 degrees.

15. A method of forming an interconnect structure, the method comprising:

forming an opening in a substrate, the opening extending into the substrate from a first surface;

forming a liner in the opening;

forming a conductive material over the liner in the opening;

recessing a second surface of the substrate to expose the conductive material, thereby forming a through via, an extending portion of the second surface of the substrate adjacent the through via extending toward a protruding end of the through via, wherein a backside surface of the liner and a backside surface of the conductive material of the through via are at a substantially same level; and

forming a dielectric layer over the second surface of the substrate, wherein the dielectric layer is over the extending portion of the second surface of the substrate, the dielectric layer physically contacting the conductive material of the through via, wherein a first vertical distance between a level of the substrate laterally adjacent a substantially planar recessed surface of the substrate and an uppermost extent of material of the substrate is greater than a second vertical distance between the uppermost extent of material of the substrate and an uppermost extent of the dielectric layer; and

planarizing the dielectric layer, the liner, and the through via such that an uppermost surface of the dielectric layer and an uppermost surface of the liner are at a substantially same level, wherein after the planarizing, an entirety of the extending portion of the second surface of the substrate is completely disposed between the liner and the outermost extent of the planarized uppermost surface of the dielectric layer.

16. The method of claim 15 , wherein the dielectric layer extends along a sidewall of the liner.

17. The method of claim 15 , wherein the dielectric layer covers the through via, and further comprising recessing the dielectric layer to expose the through via.

18. The method of claim 17 , wherein the recessing the dielectric layer further exposing the liner.

19. The method of claim 15 , wherein the second surface adjoins the liner at an angle greater than or equal to thirty degrees.

20. The method of claim 15 , further comprising forming a conductive layer over the dielectric layer, the conductive layer contacting the liner.