CIRCUITS FOR DYNAMICALLY ADAPTIVE BIT-LEVELING BY SWEEP SAMPLING WITH AUTOMATIC JITTER AVOIDANCE
A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.
1 . A circuit for performing bit leveling for a data interface, comprising:
a circuit for providing a data strobe signal;
a circuit for receiving a data bit signal, including a programmable delay line for delaying the received data bit to provide a delayed data bit signal;
at least one flip-flop for sampling the delayed data bit signal;
a bit-leveling controller circuit responsive to the delayed data bit signal and for controlling the delay of the programmable delay line; and
wherein a pattern of alternating 1's and 0's is received on a data bit signal;
wherein the delayed data bit signal is sampled with a data strobe signal at a regular interval to produce a sampled data bit signal value, the regular interval being at substantially the same frequency as the pattern of alternating 1's and 0's;
wherein from an initial delay line delay setting, the delay line delay is incrementally changed by a plurality of increments, and at each increment the sampled data bit signal value is recorded;
wherein the recorded sampled data bit signal values are analyzed to determine the width and position of strings of consecutive sampled data bits having the same signal values;
wherein a center point of one of the strings of consecutive sampled data bits is chosen to be a desired sampling point; and
wherein the programmable delay line is set to a delay setting that causes the data strobe signal to be aligned with the desired sampling point.
2 . The circuit of claim 1 wherein choosing a center point of one of the strings of consecutive sampled data bits comprises choosing a specific string of consecutive sampled data bits that requires the smallest adjustment to the programmable delay line setting with respect to the initial delay line setting.
3 . The circuit of claim 1 wherein choosing a center point of one of the strings of consecutive sampled data bits comprises choosing a specific string of consecutive sampled data bits that requires the smallest adjustment to the programmable delay line setting with respect to the position of the data strobe signal.
4 . The circuit of claim 1 wherein incrementally changing the delay line delay by a plurality of increments further comprises:
from the initial delay line delay setting, incrementally changing the delay line delay until a criteria has been satisfied indicating the changing should terminate, and recording at each increment the sampled data bit signal value.
5 . The circuit of claim 4 wherein during a first operation, a first portion of a total available delay line delay is utilized, and if a suitable position for the data strobe signal to be aligned with the desired sampling point for the data bit signal is not found, operation of the circuit according to claim 4 is performed again while utilizing at least a second portion of the total available delay line delay.
6 . The circuit of claim 1 wherein incrementally changing the delay line delay by a plurality of increments further comprises:
from the initial delay line delay setting, incrementally changing the delay line delay until a maximum delay or a minimum delay provided by the delay line has been reached, and recording at each increment the sampled data bit signal value.
7 . The circuit of claim 1 wherein incrementally changing the delay line delay by a plurality of increments further comprises:
from the initial delay line delay setting, incrementally increasing the delay line delay by a first predetermined number of increments, and recording at each increment the sampled data bit signal value; and
from the initial delay line delay setting, incrementally decreasing the delay line delay by a second predetermined number of increments, and recording at each increment the sampled data bit signal value.
8 . The circuit of claim 1 wherein choosing a center point of one of the strings of consecutive sampled data bits, further comprises choosing from strings of consecutive sampled data bits having a string length greater than a predetermined number of increments.
9 . The circuit of claim 8 wherein the predetermined number of increments represents a jitter avoidance threshold.
10 . The circuit of claim 1 wherein at least a portion of analyzing the recorded sampled data bit signal values is performed while incrementally changing the delay line delay.
11 . The circuit of claim 10 wherein the at least a portion of analyzing of the recorded sampled data bit signal values includes storing only data bit values for delay line increments where a sampled data bit value changes relative to its value at an immediately preceding delay line increment.
12 . The circuit of claim 11 wherein to avoid storing counter values, a string of data bit values is stored in memory or register locations within the bit-leveling controller circuit, wherein each location corresponds to a delay increment.
13 . The circuit of claim 1 wherein incrementally changing the delay line delay by a plurality of increments comprises changing the delay line delay by time increments that are each substantially less than the period of the pattern of alternating 1's and 's.
14 . A circuit for performing bit leveling for a data interface, comprising:
a circuit for providing a data strobe signal;
a circuit for receiving a data bit signal, including a programmable delay line for delaying the received data bit to provide a delayed data bit signal;
at least one flip-flop for sampling the delayed data bit signal;
a bit-leveling controller circuit responsive to the delayed data bit signal and for controlling the delay of the programmable delay line; and
wherein a pattern of alternating 1's and 0's is received on a data bit signal;
wherein the delayed data bit signal is sampled at multiple delay increments wherein each of the multiple delay increments is substantially less than the period of the pattern of alternating 1's and 0's;
wherein based on the sampled data bit signals, a width and position of strings of consecutive sampled data bits having the same signal values is determined; and
wherein the programmable delay line is set to a delay setting that causes the data strobe signal to be aligned with an optimum sampling point of the delayed data bit signal.
15 . The circuit of claim 14 , wherein a center point of one of the strings of consecutive sampled data bits is chosen to be the optimum sampling point.
16 . The circuit of claim 15 wherein choosing a center point of one of the strings of consecutive sampled data bits, further comprises choosing from strings of consecutive sampled data bits having a string length greater than a predetermined number of increments.
17 . The circuit of claim 16 wherein the predetermined number of increments represents a jitter avoidance threshold.
18 . The circuit of claim 14 wherein at least a portion of the determination of the width and position of strings of consecutive sampled data bits having the same signal values is performed while the delayed data bit signal is sampled at multiple delay increments.
19 . The circuit of claim 18 wherein the at least a portion of the determination of the width and position of strings of consecutive sampled data bits having the same signal values includes storing only data bit values for delay line increments where a sampled data bit value changes relative to its value at an immediately preceding delay line increment.
20 . The circuit of claim 14 wherein during a first operation a first portion of a total available delay line delay is utilized, and if a suitable position for the data strobe signal to be aligned with an optimum sampling point for the data bit signal is not found, the operation of claim 14 is performed again while utilizing at least a second portion of the total available delay line delay.