Patent Assignment
Reel/Frame 043927/0747
Release of Security Interest
Recorded: 2017-10-23
Received: 2017-10-23
Pages: 6
Assignor
MONTAGE CAPITAL II, L.P.
Executed: 2017-10-20
Assignee
UNIQUIFY, INC.
2030 FORTUNE DRIVE, SAN JOSE, CA, 95131, UNITED STATES
Covered Properties
(16)
Methods for Dynamically Adaptive Bit-Leveling by Sweep Sampling with Automatic Jitter Avoidance
Application:
14/273,455 →
Methods for Dynamically Adaptive Bit-Leveling by Incremental Sampling, Jitter Detection, and Exception Handling
Application:
14/273,416 →
Circuits for Dynamically Adaptive Bit-Leveling by Sweep Sampling with Automatic Jitter Avoidance
Application:
14/273,438 →
Continuous Adaptive Training for Data Interface Timing Calibration
Application:
14/205,208 →
Method for Operating a Circuit Including a Timing Calibration Function
Application:
14/205,254 →
Data Interface Circuit for Capturing Received Data Bits Including Continuous Calibration
Application:
14/205,239 →
Method for Operating a Data Interface Circuit Where a Calibration Controller Controls Both a Mission Path and a Reference Path
Application:
14/205,225 →
Method of Application Memory Preservation for Dynamic Calibration of Memory Interfaces
Application:
14/152,807 →
Application Memory Preservation for Dynamic Calibration of Memory Interfaces
Application:
14/152,902 →
Memory Interface Circuits Including Calibration for Cas Latency Compensation in a Plurality of Byte Lanes
Application:
14/081,806 →
Methods for Operating a Memory Interface Circuit Including Calibration for Cas Latency Compensation in a Plurality of Byte Lanes
Application:
14/081,897 →
Dynamically Calibrated DDR Memory Controller
Application:
14/023,630 →
Dynamically Adaptive Bit-Leveling for Data Interfaces
Application:
13/797,200 →
Continuous Adaptive Training for Data Interface Timing Calibration
Application:
61/777,648 →
Dynamically Calibrated Ddr Memory Controller
Application:
13/172,740 →
Ddr Memory Controller
Application:
12/157,081 →