Application memory preservation for dynamic calibration of memory interfaces
View Patent ↗A calibrating memory interface circuit is described wherein prior to a calibration operation at least a portion of application information contained in a memory circuit is moved or copied to an alternate location to preserve that information. At the completion of the calibration operation, the information is restored to the same location of the memory circuit. Thus, the calibration operation can be performed from time to time during normal operation of a system containing the memory circuit. Non-limiting examples of calibration operations are described including operations where a capture clock for a memory read circuit is calibrated, and operations where CAS latency compensation is calibrated for a DDR memory interface.
1. A memory interface circuit that is calibrated from time to time in conjunction with functional operation of a memory circuit, comprising:
one or more memory controller circuits for controlling the memory interface circuit;
one or more calibration controller circuits associated with said one or more memory controller circuits;
wherein control settings for the one or more memory controller circuits are determined and set using said one or more calibration controller circuits according to a calibration operation performed from time to time; and
wherein prior to commencing the calibration operation, a known data pattern for calibration is located in the memory circuit, and wherein if the known data pattern for calibration is not fully present in the memory circuit immediately prior to a calibration operation, at least a portion of said known data pattern for calibration is written to the memory circuit prior to the calibration operation; and
wherein prior to writing said at least a portion of the known data pattern, at least a portion of functional application data located in the memory circuit is preserved by moving said at least a portion of functional application data to an alternate location.
2. The memory interface circuit of claim 1 wherein said alternate location is located within the memory circuit.
3. The memory interface circuit of claim 1 wherein said alternate location is located outside of the memory circuit.
4. The memory interface circuit of claim 1 wherein if the known data pattern is not found in the memory circuit, a free segment in the memory circuit is located and the known data pattern is written to the free segment in the memory circuit.
5. The memory interface circuit of claim 4 wherein if the free segment in the memory circuit is not available, application memory contents located in a segment of the memory circuit are preserved to create a free segment prior to writing the known data pattern to the free segment of the memory circuit.
6. The memory interface circuit of claim 5 wherein said preservation occurs by copying at least a portion of information contained in the memory circuit to memory associated with the one or more calibration controller circuits.
7. The memory interface circuit of claim 6 wherein the memory associated with the one or more calibration controller circuits is contained within a host device also containing the one or more memory controller circuits.
8. The memory interface circuit of claim 5 , further comprising:
restoring to the memory circuit at conclusion of the calibration operation, the at least a portion of functional application data originally located in the memory circuit.
9. The memory interface circuit of claim 1 , further comprising:
restoring to the memory circuit at conclusion of the calibration operation, the at least a portion of functional application data originally located in the memory circuit.
10. The memory interface circuit of claim 1 , wherein the calibration operation includes calibrating a capture clock, wherein the capture clock is derived from a core clock originating within a host device containing the one or more memory controller circuits.
11. The memory interface circuit of claim 1 , wherein the calibration operation includes calibrating CAS latency compensation for reading a DDR memory.
12. The memory interface circuit of claim 11 , wherein calibrating CAS latency compensation for reading a DDR memory is performed in parallel for a plurality of byte lanes.
13. The memory interface circuit of claim 1 , wherein the calibration operation includes:
calibration of at least one capture clock, wherein the at least one capture clock is derived from a core clock originating within a host device containing the one or more memory controller circuits;
calibration of CAS latency compensation for reading a DDR memory; and
wherein the calibration of CAS latency compensation is performed in parallel for a plurality of byte lanes.
14. A memory interface circuit, comprising:
one or more memory controller circuits for controlling the memory interface circuit;
one or more calibration controller circuits associated with said one or more memory controller circuits;
wherein control settings for the one or more memory controller circuits are determined and set using said one or more calibration controller circuits according to a calibration operation performed from time to time;
wherein prior to the calibration operation, at least a portion of functional application data located in the memory circuit is temporarily moved or copied to an alternate location in order to preserve said at least a portion of functional application data during the calibration operation, the at least a portion of functional application data being replaced with a calibration data pattern specifically designed for use during the calibration operation; and
wherein subsequent to completion of the calibration operation, said at least a portion of functional application data is restored to its original locations in the memory circuit, thereby replacing the calibration data pattern.
15. The memory interface circuit of claim 14 , further comprising:
after the at least a portion of functional application data located in the memory circuit has been thus preserved, a known data pattern for calibration is written to one or more locations within the memory circuit.
16. The memory interface circuit of claim 15 , wherein said writing a known data pattern for calibration to one or more locations within the memory circuit is performed by the one or more calibration controller circuits.
17. The memory interface circuit of claim 15 , wherein prior to the calibration operation, the known data pattern is contained within a host device that also contains the one or more memory controller circuits.
18. The memory interface circuit of claim 14 , wherein said temporarily moving or copying at least a portion of functional application data is performed by the one or more calibration controller circuits.
19. The memory interface circuit of claim 14 , wherein said restoring said at least a portion of functional application data to its original locations is performed by the one or more calibration controller circuits.
20. The memory interface circuit of claim 14 , wherein said alternate location is contained within a host device that also contains the one or more memory controller circuits.