IP Library Granted Patent US 9,076,524
Granted Patent B2
US 9,076,524 · App. 14/283,117 · Granted Jul 7, 2015

Method of accessing a memory device

Inventor: Federico Pio (Brugherio, IT)
Assignee: Micron Technology, Inc.
G11C14/0063G11C16/26G11C16/0408G11C16/12G06F21/60G11C16/06G11C5/147G11C11/5621G11C11/5671G11C16/30G11C7/22G11C7/109
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Quick Facts
Patent No.
US 9,076,524
App. No.
14/283,117
Granted
Jul 7, 2015
Kind
B2
Abstract

A method is provided for accessing a memory device. The method includes programming data in a plurality of cells of the memory device in a first programming operation. The first programming operation uses a first memory instruction including at least one first parameter representative of at least one first threshold voltage value for said programming. The method further includes re-programming at least a portion of the data in the plurality of cells in a second programming operation. The second programming operation uses a second memory instruction including at least one second parameter representative of at least one second threshold voltage value for said re-programming, wherein said re-programming provides bit manipulation of the portion of the data.

Claims (29)

1. A method of accessing of a memory device, the method comprising:

programming data in a plurality of cells of the memory device in a first programming operation, the first programming operation using a first memory instruction comprising at least one first parameter representative of at least one first threshold voltage value for said programming; and

re-programming at least a portion of the data in the plurality of cells in a second programming operation, the second programming operation using a second memory instruction comprising at least one second parameter representative of at least one second threshold voltage value for said re-programming, wherein said re-programming provides bit manipulation of the portion of the data.

2. The method of claim 1 , wherein the first programming operation comprises selecting a first set of threshold voltage distributions to program the data.

3. The method of claim 2 , wherein the second programming operation comprises selecting a second set of threshold voltage distributions to re-program the data.

4. The method of claim 1 , wherein the second programming operation comprises programming additional bits.

5. The method of claim 4 , wherein the second programming operation changes error correction code (ECC) bits.

6. The method of claim 1 , wherein the at least one first threshold voltage value comprises two first threshold voltage values, the at least one second threshold voltage value comprises two second threshold voltage values.

7. The method of claim 6 , further comprising reading the data programmed in the first programming operation using a read voltage value between the two first threshold voltage values.

8. The method of claim 6 , further comprising reading the portion of the data re-programmed in the second programming operation using a read voltage value between the two second threshold voltage values.

9. The method of claim 1 , further comprising re-programming at least a second portion of the data in the plurality of cells in a third programming operation, the third programming operation using a third memory instruction comprising at least one third parameter representative of at least one third threshold voltage value for said re-programming.

10. The method of claim 9 , wherein the at least one first threshold voltage value comprises two first threshold voltage values, the at least one second threshold voltage value comprises two second threshold voltage values, and the at least one third threshold voltage value comprises two third threshold voltage values.

11. The method of claim 10 , further comprising reading the data programmed in the first programming operation using a read voltage value between the two first threshold voltage values.

12. The method of claim 10 , further comprising reading the portion of the data re-programmed in the second programming operation using a read voltage value between the two second threshold voltage values.

13. The method of claim 10 , further comprising reading the second portion of the data re-programmed in the third programming operation using a read voltage value between the two third threshold voltage values.

14. The method of claim 10 , wherein the two second threshold voltage values comprise one of the two first threshold voltage values.

15. The method of claim 10 , wherein the two third threshold voltage values comprise one of the two second threshold voltage values.

16. A memory device comprising:

a plurality of memory cells; and

circuitry to:

program data in the plurality of memory cells in a first programming operation using a first memory instruction comprising at least one first parameter representative of at least one first threshold voltage value; and

re-program at least a portion of the data in the plurality of memory cells in a second programming operation using a second memory instruction comprising at least one second parameter representative of at least one second threshold voltage value.

17. The memory device of claim 16 , wherein the circuitry provides bit manipulation of the portion of the data by the second programming operation.

18. A memory system comprising:

a memory device comprising a plurality of memory cells and a memory controller to:

program data in the plurality of memory cells in a first programming operation using a first memory instruction comprising at least one first parameter representative of at least one first threshold voltage value; and

re-program at least a portion of the data in the plurality of memory cells in a second programming operation using a second memory instruction comprising at least one second parameter representative of at least one second threshold voltage value; and

a processor configured to host one or more applications and to provide access to said plurality of memory cells.

19. The memory system of claim 18 , wherein the memory controller provides bit manipulation of the portion of the data by the second programming operation.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (3)
Division 13770881 · Feb 19, 2013
Continuation 12949728 · Nov 18, 2010
Related Publication 20140250280A1 · Sep 4, 2014