IP Library Granted Patent US 9,577,192
Granted Patent B2
US 9,577,192 · App. 14/283,539 · Granted Feb 21, 2017

Method for forming a metal cap in a semiconductor memory device

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Quick Facts
Patent No.
US 9,577,192
App. No.
14/283,539
Granted
Feb 21, 2017
Kind
B2
Abstract

Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap above a recessed cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments.

Claims (30)

1. A method for fabricating a semiconductor memory device comprising:

performing a chemical-mechanical planarization to form a cell structure entirely recessed in a template layer, wherein a top surface of the cell structure is below a top surface of the template layer, forming a recess; and

selectively depositing a material in the recess to form a cap above the cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments,

wherein the cap is a metal cap, and

wherein the cell structure includes a top electrode and an active cell material.

2. The method of claim 1 , wherein selectively depositing the material to form a cap further comprises:

using one of chemical vapor deposition, atomic layer deposition or selective electroless plating for deposition.

3. The method of claim 1 , further comprising removing the cap using a dry etch method.

4. The method of claim 1 , wherein the cell structure is formed in a trench in the template layer.

5. The method of claim 4 , wherein the cap is formed using one of W, Ti, or Co.

6. The method of claim 1 , further comprising a bottom electrode formed below the cell structure.

7. The method of claim 6 , further comprising a transistor connected to the bottom electrode.

8. The method of claim 6 , wherein the cap covers an entire surface of the top electrode.

9. The method of claim 1 , wherein the top electrode is formed over the active cell material.

10. The method of claim 1 , wherein the cap is deposited in the recess such that it covers an entire surface of the top electrode.

11. A method for fabricating a semiconductor memory device comprising:

performing a chemical-mechanical planarization to form a cell structure entirely recessed in a template layer, wherein a top surface of the cell structure is below a top surface of the template layer, forming a recess; and

selectively depositing a material in the recess to form a cap above the cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments,

wherein the cell structure includes a top electrode and an active cell material, and

wherein the cap covers an entirety of a surface that includes a portion of the top electrode and a portion of the active cell material.

12. The method of claim 11 , further comprising a bottom electrode formed below the cell structure.

13. The method of claim 12 , further comprising a transistor connected to the bottom electrode.

14. The method of claim 11 , wherein selectively depositing the material to form a cap further comprises:

using one of chemical vapor deposition, atomic layer deposition or selective electroless plating for deposition.

15. The method of claim 11 , further comprising removing the cap using a dry etch method.

16. The method of claim 11 , wherein the cell structure is formed in a trench in a template layer.

17. The method of claim 11 , wherein the cap is a metal cap.

18. The method of claim 17 , wherein the cap is formed using one of W, Ti, or Co.

19. The method of claim 1 , wherein the cap is formed using one of W, Ti, or Co.

20. The method of claim 1 , wherein the cap covers an entirety of a surface that includes a portion of the top electrode and a portion of the active cell material.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE INCORRECT APPLICATION NUMBER 14/572221 AND REPLACE IT WITH 14/527221 PREVIOUSLY RECORDED AT REEL: 040815 FRAME: 0649. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 27, 2022
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 058875/0887 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED ON REEL 039635 FRAME 0495. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 5, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 040815/0649 →
CHANGE OF NAME Recorded Aug 9, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 039635/0495 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2014
From: BALAKRISHNAN, MURALIKRISHNAN; BIAN, ZAILONG; DAMARLA, GOWRISANKAR; LI, HONGQI; LU, JIN; RAMALINGAM, SHYAM; ZHU, XIAOYUN
To: SONY CORPORATION
Reel/Frame 032948/0449 →