IP Library Granted Patent US 9,299,644
Granted Patent B1
US 9,299,644 · App. 14/285,601 · Granted Mar 29, 2016

Integrated circuit packaging system with routed circuit lead array and method of manufacture thereof

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Quick Facts
Patent No.
US 9,299,644
App. No.
14/285,601
Granted
Mar 29, 2016
Kind
B1
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a top with a depression; applying a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom; forming a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and connecting an integrated circuit to the terminal through the trace.

Claims (27)

1. An integrated circuit packaging system comprising:

a terminal having a top with a plateau and a depression;

a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom, and the dielectric material directly above a peripheral portion of the plateau;

a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and

an integrated circuit connected to the terminal through the trace.

2. The system as claimed in claim 1 further comprising:

a die pad adjacent to the terminal;

a contact layer below the die pad;

a perimeter trace around the die pad; and

wherein:

the integrated circuit is attached to the die pad.

3. The system as claimed in claim 1 wherein the trace extends beyond the integrated circuit from below the integrated circuit.

4. The system as claimed in claim 1 further comprising multiple traces terminating at a non-uniform distance from the integrated circuit.

5. The system as claimed in claim 1 wherein the trace extends below the integrated circuit from the terminal beyond the integrated circuit.

6. A system as claimed in claim 1 wherein:

the terminal has a maximum width and has a bottom portion with a dent extending from the maximum width to a base;

the top of the terminal has the depression extends from the plateau to the maximum width;

the dielectric material is in direct contact with the plateau and extends to the maximum width;

the gap exposes a portion of the plateau therefrom; and

the trace is in direct contact with the plateau; and

further comprising:

a contact layer formed directly to the base of the terminal; and

an encapsulation encapsulating the trace and the integrated circuit.

7. The system as claimed in claim 6 wherein the contact layer is formed directly to a portion of the dent of the terminal near the base leaving a portion of the dent near the maximum width exposed.

8. The system as claimed in claim 6 further comprising a dimpled surface formed in the terminal centered in the base.

9. The system as claimed in claim 6 further comprising solder balls below the base and attached to the contact layer.

10. The system as claimed in claim 6 wherein the integrated circuit is connected to the terminal with a bond wire or with a solder ball.

Assignments (2)
CHANGE OF NAME Recorded Jul 27, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 039492/0956 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2016
From: DO, BYUNG TAI; TRASPORTO, ARNEL SENOSA; CAMACHO, ZIGMUND RAMIREZ
To: STATS CHIPPAC LTD.
Reel/Frame 039262/0285 →