High voltage bootstrap gate driving apparatus
A high voltage bootstrap gate driving apparatus is provided. The gate driving apparatus includes a high-end transistor, a low-end transistor, a buffer, a boost capacitor, and a high voltage depletion transistor. The high-end transistor receives a first power voltage. The buffer provides a high-end driving signal to the high-end transistor according to a bias voltage. The boost capacitor is serial coupled between a base voltage and a bias voltage. A first end of the depletion transistor is coupled to a second power voltage, a second end of the depletion transistor is coupled to the bias voltage, and a control end of the depletion transistor receives the reference ground voltage.
1. A high voltage bootstrap gate driving apparatus, comprising:
a high-end transistor, having a first end, a second end, and a control end, wherein the first end of the high-end transistor receives a first power voltage;
a low-end transistor, having a first end, a second end, and a control end, wherein the first end of the low-end transistor is coupled to the second end of the high-end transistor, and the second end of the low-end transistor is coupled to a reference ground voltage;
a buffer, providing a high-end driving signal to the control end of the high-end transistor according to a bias voltage, and providing a low-end driving signal to the control end of the low-end transistor;
a boost capacitor, serial coupled between a base voltage and the bias voltage, wherein the base voltage is produced at the second end of the high-end transistor;
a depletion transistor, having a first end, a second end, and a control end, wherein the first end of the depletion transistor is coupled to a second power voltage, the second end of the depletion transistor is coupled to the bias voltage, and the control end of the depletion transistor receives the reference ground voltage,
wherein the buffer, the high-end transistor, the low-end transistor, the boost capacitor and the depletion transistor are disposed in an integrated circuit,
wherein as the low-end transistor is conductive according to the low-end driving signal, the high-end transistor is disconnected, and the second power voltage charges the boost capacitor through the depletion transistor, so that the bias voltage is equal to a threshold turn-off voltage of the depletion transistor, wherein when the high-end transistor is conductive according to the high-end driving signal, the low-end transistor is disconnected, and the bias voltage is pulled up to be equal to the first power voltage plus the threshold turn-off voltage.
2. The high voltage bootstrap gate driving apparatus as claimed in claim 1 , wherein the depletion transistor is an N-type depletion transistor or an N-type junction field effect transistor.
3. The high voltage bootstrap gate driving apparatus as claimed in claim 2 , wherein a base of the depletion transistor is coupled to the reference ground voltage.
4. The high voltage bootstrap gate driving apparatus as claimed in claim 1 , wherein the high-end transistor and the low-end transistor are N-type transistors.
5. The high voltage bootstrap gate driving apparatus as claimed in claim 1 , wherein the buffer comprises:
a high-end buffer, coupled to the second end of the depletion transistor, the control end of the high-end transistor, and the second end of the high-end transistor, wherein the high-end buffer adjusts a voltage level of the high-end driving signal according to the bias voltage; and
a low-end buffer, coupled to the control end of the low-end transistor, and providing the low-end driving signal.
6. The high voltage bootstrap gate driving apparatus as claimed in claim 5 , further comprising:
a core circuit, coupled to the high-end buffer and the low-end buffer, the core circuit provides a high-end control signal and a low-end control signal to the high-end buffer and the low-end buffer respectively,
wherein the high-end buffer and the low-end buffer produce the high-end driving signal and the low-end driving signal respectively according to the high-end control signal and the low-end control signal respectively.
7. The high voltage bootstrap gate driving apparatus as claimed in claim 1 , wherein both the high-end driving signal and the low-end driving signal are pulse width modulation signals.
8. The high voltage bootstrap gate driving apparatus as claimed in claim 1 , wherein a voltage level of the first power voltage is greater than a voltage level of the second power voltage.
9. The high voltage bootstrap gate driving apparatus as claimed in claim 1 , wherein a reverse breakdown voltage of the depletion transistor is greater than a voltage level of the first power voltage plus a voltage level of a threshold turn-off voltage of the depletion transistor.
10. A high voltage bootstrap gate driving apparatus, comprising:
a high-end transistor, having a first end, a second end, and a control end, wherein the first end of the high-end transistor receives a first power voltage;
a low-end transistor, having a first end, a second end, and a control end, wherein the first end of the low-end transistor is coupled to the second end of the high-end transistor, and the second end of the low-end transistor is coupled to a reference ground voltage;
a buffer, providing a high-end driving signal to the control end of the high-end transistor according to a bias voltage, and providing a low-end driving signal to the control end of the low-end transistor;
a boost capacitor, serial coupled between a base voltage and the bias voltage, wherein the base voltage is produced at the second end of the high-end transistor;
a depletion transistor, having a first end, a second end, and a control end, wherein the first end of the depletion transistor is coupled to a second power voltage, the second end of the depletion transistor is coupled to the bias voltage, and the control end of the depletion transistor receives the reference ground voltage,
wherein the buffer, the high-end transistor, the low-end transistor, the boost capacitor and the depletion transistor are disposed in an integrated circuit,
wherein a reverse breakdown voltage of the depletion transistor is greater than a voltage level of the first power voltage plus a voltage level of a threshold turn-off voltage of the depletion transistor.