IP Library › Granted Patent US 9,313,894
Granted Patent B2
US 9,313,894 · App. 14/295,721 · Granted Apr 12, 2016

Wiring substrate and manufacturing method of wiring substrate

Inventors: Takayuki Kiwanami (Nagano, JP); Junji Sato (Nagano, JP); Katsuya Fukase (Nagano, JP)
Assignee: Shinko Electric Industries Co., Ltd.
H05K1/185H05K1/182H05K3/4697H05K1/113H05K1/18H05K3/4602H05K3/4644H05K2201/10636Y02P70/611
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Quick Facts
Patent No.
US 9,313,894
App. No.
14/295,721
Granted
Apr 12, 2016
Kind
B2
Abstract

A wiring substrate includes a core, a first wiring layer formed on a first surface of the core, a second wiring layer formed on a second surface of the core, and an electronic component partially accommodated in the cavity and including a projected portion projected from the first opening of the core. A first insulating layer covers a side surface of the electronic component and the first surface of the core and fills a portion of the cavity. A second insulating layer covers the first insulating layer. A third insulating layer covers the second surface of the core. The remainder of the cavity that is not filled with the first insulating layer is filled with the third insulating layer.

Claims (22)

1. A wiring substrate comprising:

a core including a first surface, a second surface, and a cavity, wherein the second surface is located at an opposite side of the first surface, and the cavity extends through the core in a thicknesswise direction and includes a first opening in the first surface and a second opening in the second surface;

a first wiring layer formed on the first surface of the core;

a second wiring layer formed on the second surface of the core;

an electronic component partially accommodated in the cavity and including a projected portion projected from the first opening of the core;

a first insulating layer covering over the first wiring layer and the first surface of the core, wherein the first insulating layer covers at least a portion of a side surface of the electronic component and fills a portion of the cavity;

a second insulating layer that covers a first surface of the first insulating layer;

a plurality of first via wires each extending through the first and second insulating layers in the thicknesswise direction, wherein the first wiring layer and the electronic component are electrically connected to different ones of the plurality of first via wires;

a third insulating layer that covers the second surface of the core, wherein the remainder of the cavity that is not filled with the first insulating layer is filled with the third insulating layer;

a third wiring layer formed on the second insulating layer and electrically connected to the electronic component and the first wiring layer through the different ones of the plurality of first via wires;

a second via wire that extends through the third insulating layer; and

a fourth wiring layer formed on the third insulating layer and electrically connected to the second wiring layer through the second via wire.

2. The wiring substrate according to claim 1 , wherein a thickness of the second insulating layer over the first wiring layer is equal to a thickness of the third insulating layer over the second wiring layer.

3. The wiring substrate according to claim 1 , wherein the first insulating layer entirely covers a side surface of the projected portion of the electronic component.

4. The wiring substrate according to claim 1 , wherein

the electronic component includes surfaces located in the cavity, and

the first insulating layer entirely covers the surfaces of the electronic component located in the cavity.

5. The wiring substrate according to claim 1 , wherein the first insulating layer includes a first portion sandwiched between the first wiring layer and the second insulating layer.

6. The wiring substrate according to claim 5 , wherein

the first insulating layer includes a second portion sandwiched between the first surface of the core and the second insulating layer,

the first portion of the first insulating layer has a first thickness, and

the second portion of the first insulating layer has a second thickness greater than the first thickness.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2014
From: KIWANAMI, TAKAYUKI; SATO, JUNJI; FUKASE, KATSUYA
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 033106/0933 →
Priority Claims (1)
JP 2013-121872 · Jun 10, 2013 · national
Continuity (1)
Related Publication 20140360760A1 · Dec 11, 2014