IP Library Granted Patent US 9,378,165
Granted Patent B2
US 9,378,165 · App. 14/297,200 · Granted Jun 28, 2016

Inter-bus communication interface device

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Quick Facts
Patent No.
US 9,378,165
App. No.
14/297,200
Granted
Jun 28, 2016
Kind
B2
Abstract

There is provided an inter-bus communication interface device capable of efficiently performing transfer of data between a plurality of devices connected to different buses, respectively. When communication data is transmitted, a first device writes the communication data into a buffer, whereas when communication control information is transmitted, the first device writes the communication control information into a register. A control circuit passes the communication data stored in the buffer to a second device, and passes the communication control information stored in the register to a second device.

Claims (40)

1. An interface device, comprising:

a buffer coupled to a first bus and a second bus and configured to store communication data received via the first bus;

a register coupled to the first bus and the second bus in parallel to the buffer, wherein the register is configured to store communication control information received via the first bus, wherein the control information is used to process the communication data;

a status register configured to store a status of the buffer and the register; and

a control circuit configured to transfer the communication data and the communication control information via the second bus based on the status stored in the status register.

2. The interface device of claim 1 , wherein the status comprises information indicating whether the status register indicates the buffer has data stored therein and new information has been written to the register.

3. The interface device of claim 1 , wherein the communication control information comprises data end information indicating the end of the communication data.

4. The interface device of claim 1 , wherein the control circuit is further configured to output an interrupt signal after the communication control information is stored in the register.

5. The interface device of claim 1 , wherein the control circuit is further configured to update the status when new data is stored in the register, or when data in the buffer is read.

6. The interface device of claim 1 , wherein the buffer comprises a first-in first-out buffer.

7. The interface device of claim 1 , wherein the buffer comprises a plurality of buffer areas configured to store additional communication data.

8. The interface device of claim 1 , further comprising:

an additional buffer coupled between the first and second bus and configured to store additional communication information received via the second bus; and

an additional register coupled to the first and second bus and configured to store additional control information received via the second bus, wherein the additional control information is used to process the additional communication data.

9. The interface device of claim 8 , wherein status register is further configured to store an additional status of the additional buffer and the additional register.

10. The interface device of claim 9 , wherein the control circuit is further configured to transfer the additional communication data and the additional communication control information via the first bus based on the additional status.

11. A method, comprising:

receiving communication data and communication control information via a first bus;

storing the communication data in a buffer coupled to the first bus and a second bus;

storing the communication control information in a register coupled to the first bus and the second bus in parallel to the buffer;

receiving a transmit request; and

transmitting the communication data and the communication control information via the second bus in response to the transmit request.

12. The method of claim 11 , further comprising:

updating a status in a status register in response to receiving the communication data and the communication control information.

13. The method of claim 12 , further comprising:

transmitting a request signal via the second bus when the status indicates that the buffer is full.

14. The method of claim 12 , further comprising:

updating the status in the status register in response to transmitting the communication data and the communication control information via the second bus.

15. The method of claim 11 , further comprising:

transmitting an interrupt signal via the second bus in response to storing the communication control information in the register.

16. The method of claim 11 , wherein the communication control information comprises data end information indicating the end of the communication data.

17. The method of claim 11 , further comprising:

receiving additional communication data and additional control information via a second bus;

storing the additional communication data in an additional buffer coupled to the first bus and the second bus;

storing the additional communication control information in an additional register coupled to the first bus and the second bus.

18. The method of claim 17 , further comprising:

updating a status in response to receiving the additional communication data and the additional control information.

19. The method of claim 17 , further comprising:

transmitting the additional communication data and the additional control information via the first bus.

20. The method of claim of claim 17 , further comprising: updating a status in response to transmitting the additional communication data and the additional control information.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2021
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 058346/0597 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2021
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 058340/0045 →
RELEASE OF SECURITY INTEREST Recorded Sep 14, 2021
From: MUFG UNION BANK, N.A.,
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 057501/0144 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2015
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 035902/0641 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2014
From: IIZUKA, KENICHI; TOSHIMORI, KUMIKO; MIKAMI, MACHIKO
To: SPANSION LLC
Reel/Frame 033168/0188 →