Apparatus and method for forming semiconductor contacts
View Patent ↗A method for forming semiconductor contacts comprises forming a germanium fin structure over a silicon substrate, depositing a doped amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin structure and performing a solid phase epitaxial regrowth process on the amorphous silicon layer at a second temperature, wherein the second temperature is lower than the melting point of the germanium fin structure.
1. An apparatus comprising:
a substrate formed of a first material;
an isolation region formed in the substrate;
a fin structure formed over the substrate, wherein the fin structure is formed of a second material, and wherein the fin structure protrudes above a top surface of the isolation region, and wherein the fin structure comprises:
a channel connected between a first drain/source region and a second drain/source region;
a gate electrode wrapping the channel of the fin structure;
a first barrier-less contact region formed over the first drain/source region; and
a first metal contact formed over the first barrier-less contact region.
2. The apparatus of claim 1 , wherein:
the substrate is formed of silicon; and
the fin structure is formed of germanium.
3. The apparatus of claim 2 , wherein:
the fin structure is formed of n-type germanium.
4. The apparatus of claim 2 , further comprising:
a p-type silicon germanium layer formed between the substrate and the fin structure, wherein the p-type silicon germanium layer is surrounded by the isolation region.
5. The apparatus of claim 1 , further comprising:
a second barrier-less contact region formed over the second drain/source region; and
a second metal contact formed over the second barrier-less contact region.
6. The apparatus of claim 5 , wherein:
the first barrier-less contact region is formed of N+ silicon.
7. The apparatus of claim 1 , wherein:
the first drain/source region, the second drain/source region and the channel form an n-type FinFET.
8. The apparatus of claim 1 , wherein the isolation region is a shallow trench isolation structure.
9. A device comprising:
a germanium fin structure over a silicon substrate, wherein the germanium fin structure comprises a channel connected between a first drain/source region and a second drain/source region;
a first silicon layer over the first drain/source region;
a second silicon layer over the second drain/source region;
a first drain/source metal contact on the first silicon layer; and
a second drain/source metal contact on the second silicon layer.
10. The device of claim 9 , wherein:
the germanium fin structure is formed of n-type germanium.
11. The device of claim 9 , wherein:
the first silicon layer is formed of n-type silicon; and
the second silicon layer is formed of n-type silicon.
12. The device of claim 9 , wherein:
the first silicon layer wraps the first drain/source region around three sides; and
the second silicon layer wraps the second drain/source region around three sides.
13. The device of claim 9 , further comprising:
a p-type silicon germanium region over the silicon substrate; and
an isolation region over the silicon substrate, wherein the p-type silicon germanium region is partially embedded in the isolation region.
14. The device of claim 13 , wherein:
the germanium fin structure is over the p-type silicon germanium region.
15. A structure comprising:
an n-type germanium fin over a p-type silicon germanium region, wherein the n-type germanium fin comprises a drain region, a source region and a channel coupled between the drain region and the source region, and wherein the p-type silicon germanium region is over a substrate;
a gate structure over the channel, wherein the gate structure comprises:
a gate dielectric layer; and
a gate electrode layer formed over the gate dielectric layer;
a first silicon layer over the drain region; and
a second silicon layer over the source region.
16. The structure of claim 15 , further comprising:
a first metal contact on the first silicon layer; and
a second metal contact on the second silicon layer.
17. The structure of claim 15 , further comprising:
a dielectric layer over the substrate, wherein the first silicon layer and the second silicon layer are embedded in the dielectric layer.
18. The structure of claim 15 , further comprising:
an isolation region between the dielectric layer and substrate, wherein a lower portion of the p-type silicon germanium region is surrounded by the isolation region.
19. The structure of claim 18 , wherein:
a bottom surface of the n-type germanium fin is higher than a top surface of the isolation region.
20. The structure of claim 19 , wherein:
the first silicon layer and the second silicon layer are formed of N+ silicon.