Method and structure for protecting gates during epitaxial growth
Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth (“mouse ears”) on the transistor gate is prevented.
1. A method of forming a semiconductor structure, comprising:
forming a gate on a semiconductor structure;
forming a hardmask layer on the gate;
forming inner spacers adjacent to the gate;
forming outer spacers adjacent to the inner spacers;
forming stressor cavities adjacent to the gate after forming the outer spacers;
recessing a portion of the inner spacers of the gate to form divots extending below a top surface of the gate;
filling the divots with an epitaxial growth inhibiting material selected from silicon carbon nitride or silicon oxycarbide, wherein the epitaxial growth material extends from below the top surface of the gate to above the top surface of the gate, thereby inhibiting epitaxial growth on the gate;
performing an etch back of the epitaxial growth inhibiting material to form an upper spacer having a height substantially similar to a height of the outer spacers and to expose the substrate; and
filling the stressor cavities with a stressor material after performing the etch back.
2. The method of claim 1 , wherein recessing a portion of the inner spacers performed with a chemical oxide removal process.
3. The method of claim 1 , wherein recessing a portion of the inner spacers further comprises performing a selective etch process.
4. The method of claim 1 , wherein filling the divots is performed via an atomic layer deposition process.
5. The method of claim 1 , wherein recessing the portion of the inner spacers of the gate to form divots extending below the top surface of the gate further comprises recessing the portion of the inner spacers of the gate for forming divots extending below the top surface of the gate by an amount in the range of about 5% to about 50% of the height of the gate.
6. The method of claim 1 , wherein forming the inner spacers comprises depositing silicon oxide.
7. The method of claim 1 , wherein forming the outer spacers comprises depositing silicon nitride.
8. The method of claim 1 , wherein filling the stressor cavities with the stressor material, comprises filling the stressor cavities with silicon germanium.
9. The method of claim 1 , wherein forming stressor cavities comprises forming a sigma cavity.
10. A method, comprising:
forming a transistor gate on a semiconductor substrate;
forming a lower inner spacer disposed adjacent to a lower portion of the transistor gate below a top surface of the gate;
forming an upper inner spacer disposed adjacent to an upper portion of the transistor gate and in contact with the lower inner spacer, the upper inner spacer extending from below the top surface of the gate to above the top surface of the gate, the upper inner spacer being formed from an epitaxial growth inhibiting material selected from silicon carbon nitride or silicon oxycarbide to inhibit epitaxial growth on the gate; and
forming an outer spacer disposed adjacent the lower inner spacer and the upper inner spacer;
forming a stressor cavity adjacent to the gate after forming the outer spacer;
etching back the epitaxial growth inhibiting material to bring an upper surface of the upper inner spacer to a height substantially similar to a height of the outer spacers; and
filling the stressor cavity with a stressor material after etching back.
11. The method of claim 10 , wherein forming an upper inner spacer further comprises forming the upper inner spacer extending below the top surface of the gate by an amount in the range of about 5% to about 50% of the height of the gate.
12. The method of claim 10 , wherein forming the inner spacers further comprises depositing silicon oxide.
13. The method of claim 10 , wherein forming the outer spacer further comprises depositing silicon nitride.
14. The method of claim 10 , wherein filling the stressor cavities with the stressor material, further comprises filling the stressor cavities with silicon germanium.