Bump structures for multi-chip packaging

1. A multi-chip package comprising:

a substrate having a plurality of first bump structures, wherein a pitch between adjacent first bump structures of the plurality of first bump structures is uniform across a surface of the substrate;

a first chip bonded to the substrate, wherein the first chip comprises a plurality of second bump structures, and the plurality of second bump structures are bonded to a first set of first bump structures of the plurality of first bump structures; and

a second chip bonded to the substrate, wherein the second chip comprises a plurality of third bump structures, and the plurality of third bump structures are bonded to a second set of first bump structures of the plurality of first bump structures, wherein a pitch between adjacent second bump structures of the plurality of second bump structures is different from a pitch between adjacent third bump structures of the plurality of third bump structures, wherein a pitch of the first set of first bump structures of the plurality of first bump structures is substantially equal to a pitch of the second set of second bump structures of the plurality of first bump structures.

2. The multi-chip package of claim 1 , wherein at least one third bump structure of the plurality of third bump structures covers an entire sidewall of each first bump structure of the second set of first bump structures.

3. The multi-chip package of claim 1 , wherein first bump structures of the second set of first bump structures are arranged in a triangular pattern, a quadrilateral pattern, a pentagonal pattern, a hexagonal pattern, or a quincunx pattern.

4. The multi-chip package of claim 1 , wherein at least one third bump structure of the plurality of third bump structures comprises:

a diffusion barrier layer;

a copper layer over the diffusion barrier layer; a metal layer over the copper layer; and

a solder layer over the metal layer.

5. The multi-chip package of claim 4 , wherein the metal layer comprises nickel.

6. The multi-chip package of claim 4 , wherein a thickness of the copper layer ranges from 5 microns (μm) to 50 μm.

7. The multi-chip package of claim 4 , wherein a thickness of the solder layer ranges from about 15 μm to 60 μm.

8. The multi-chip package of claim 4 , wherein a thickness of the solder layer is greater than a thickness of the copper layer.

9. The multi-chip package of claim 1 , wherein each first bump structure of the plurality of first bump structures is a copper post, and each third bump structure of the plurality of third bump structures is a solder bump.

10. A multi-chip package comprising:

a substrate having a plurality of first bump structures;

a first chip bonded to the substrate, wherein the first chip comprises a plurality of second bump structures, and at least one second bump structure of the plurality of second bump structures covers an entirety of each sidewall of at least two first bump structures of the plurality of first bump structures, the at least two first bump structures being separated by a passivation layer; and

a second chip bonded to the substrate, wherein the second chip comprises a plurality of third bump structures, and the plurality of third bump structures are bonded to a set of first bump structures of the plurality of first bump structures.

11. The multi-chip package of claim 10 , wherein at least one second bump structure of the plurality of second bump structures comprises:

an under bump metallurgy (UBM) layer; and

a solder layer in direct contact with the UBM layer.

12. The multi-chip package of claim 10 , wherein at least one first bump structure of the plurality of first bump structures comprises:

a diffusion barrier layer;

a copper layer over the diffusion barrier layer; and a nickel-containing layer over the copper layer.

13. The multi-chip package of claim 12 , wherein the nickel-containing layer covers sidewalls of the copper layer.

14. The multi-chip package of claim 12 , wherein the at least one first bump structure of the plurality of first bump structures further comprises a solder layer over the nickel-containing layer.

15. The multi-chip package of claim 14 , wherein a thickness of the copper layer is greater than a thickness of the solder layer.

16. A multi-chip package comprising:

a substrate having a plurality of first bump structures, wherein a pitch between adjacent first bump structures of the plurality of first bump structures is uniform across a surface of the substrate;

a first chip bonded to the substrate, wherein the first chip comprises a plurality of second bump structures, and the plurality of second bump structures are bonded to a first set of first bump structures of the plurality of first bump structures such that at least one second bump structure of the plurality of second bump structures covers an entirety of sidewalls of at least two first bump structures of the plurality of first bump structures, the at least two first bump structures being separated by a passivation layer; and

a second chip bonded to the substrate, wherein the second chip comprises a plurality of third bump structures, and the plurality of third bump structures are bonded to a second set of first bump structures of the plurality of first bump structures.

17. The multi-chip package of claim 16 , wherein each first bump structure of the plurality of first bump structures comprises:

an under bump metallurgy (UBM) layer; a copper layer over the UBM layer; and a metal layer over the copper layer.

18. The multi-chip package of claim 17 , wherein the metal layer covers sidewalls of the UBM layer.

19. The multi-chip package of claim 17 , wherein the metal layer separates the copper layer from a solder material a corresponding second bump structure of the plurality of second bump structures.

20. The multi-chip package of claim 16 , wherein a pitch of the plurality of second bump structures is different from a pitch of the plurality of third bump structures.