Apparatuses, devices and methods for sensing a snapback event in a circuit
Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.
1. An apparatus comprising:
a sense circuit responsive to a snapback event occurring in a memory cell and configured to generate a feedback signal to initiate a change in an electric potential applied to the memory cell; and
wherein the memory cell is capable of producing a plurality of snapback event levels, and wherein the sense circuit is configured to differentiate between the plurality of snapback event levels to determine a state of the memory cell.
2. The apparatus of claim 1 , wherein the memory cell comprises a first node and a second node, wherein the second node exhibits a lower capacitance than the first node, and wherein the sense circuit is coupled to and responsive to a voltage signal at the second node.
3. The apparatus of claim 2 , wherein the voltage signal at the second node is due to an electric charge released from the memory cell undergoing the snapback event being placed on a parasitic capacitance associated with the second node.
4. The apparatus of claim 1 , wherein the sense circuit is configured to generate the feedback signal in response to the voltage signal exceeding a threshold voltage level.
5. The apparatus of claim 1 , wherein the sense circuit is configured to differentiate between the plurality of snapback event levels to determine the state of the memory cell by at least one of:
selecting the electric potential for a particular one of the plurality of snapback event levels; or
setting a threshold voltage level to determine that the particular one of the plurality of snapback events levels has occurred.
6. The apparatus of claim 1 , wherein the electric potential is removed after a period of time has passed without the sense circuit detecting the snapback event occurring in the memory cell.
7. A memory device, comprising:
an interface to receive a program command;
a memory cell to receive a programming potential in response to the program command; and
a sense circuit to provide a feedback signal to reduce the programming potential in response to a snapback event occurring in the memory cell,
wherein the sense circuit is configured to provide the feedback signal to reduce at least one of an amount of time that the programming potential is applied to the memory cell or a power consumption of the memory.
8. A memory device comprising:
an interface to receive a program command;
a memory cell to receive a programming potential in response to the program command, and
a sense circuit to provide a feedback signal to reduce the programming potential in response to a snapback event occurring in the memory cell,
wherein the memory cell is capable of producing a plurality of snapback event levels, wherein the sense circuit is configured to differentiate between the plurality of snapback event levels to determine a state of the memory cell, and wherein the program command is based on the state of the memory cell.
9. The memory device of claim 8 , wherein the sense circuit is configured to differentiate between the plurality of snapback event levels to determine the state of the memory cell comprises by at least one of:
selecting an electric potential to be applied to the memory cell for a particular one of the plurality of snapback event levels; or
setting a threshold voltage level to determine that the particular one of the plurality of snapback event levels has occurred.
10. The memory device of claim 9 , wherein the electric potential is removed after a period has passed without the sense circuit detecting the snapback event occurring in the memory cell.