Capacitor arrangements using a resistive switching memory cell structure
View Patent ↗In one embodiment, a capacitive circuit can include: (i) a resistive storage element having a solid electrolyte, a first electrode coupled to a first side of the solid electrolyte, and a second electrode coupled to a second side of the solid electrolyte; (ii) the resistive storage element being configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction to form a conductive path between the first and second electrodes, and being configured to be erased to a high resistance state by application of an erase voltage in a reverse bias direction to substantially dissolve the conductive path; and (iii) a first capacitor having the first electrode coupled to a first side of a first oxide layer, and a third electrode coupled to a second side of the first oxide layer.
1. A capacitive circuit, comprising:
a) a boundary cell having a resistive storage element that comprises a solid electrolyte, a first electrode coupled to a first side of the solid electrolyte, and a second electrode coupled to a second side of the solid electrolyte;
b) a plurality of resistive switching memory cells that form a functioning memory array, wherein the boundary cell is outside of the functioning memory array;
c) the resistive storage element being configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction to form a conductive path between the first and second electrodes, and being configured to be erased to a high resistance state by application of an erase voltage in a reverse bias direction to substantially dissolve the conductive path; and
d) a first capacitor comprising the first electrode coupled to a first side of a first oxide layer, and a third electrode coupled to a second side of the first oxide layer.
2. The capacitive circuit of claim 1 , wherein the first oxide layer comprises a metal oxide.
3. The capacitive circuit of claim 1 , wherein the solid electrolyte comprises:
a) an injection barrier layer (IBL) coupled to the first electrode; and
b) a metal oxide coupled to the second electrode.
4. The capacitive circuit of claim 1 , further comprising a second capacitor having the third electrode coupled to a first side of a second oxide layer, and a fourth electrode coupled to a second side of the second oxide layer.
5. The capacitive circuit of claim 1 , wherein the first electrode comprises tungsten.
6. The capacitive circuit of claim 1 , wherein the resistive storage element comprises a conductive bridging random-access memory (CBRAM) storage element.
7. A capacitive circuit, comprising:
a) a plurality of resistive storage elements, wherein each resistive storage element comprises a solid electrolyte, a first electrode coupled to a first side of the solid electrolyte, and a second electrode coupled to a second side of the solid electrolyte;
b) each resistive storage element being configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction to form a conductive path between the first and second electrodes, and being configured to be erased to a high resistance state by application of an erase voltage in a reverse bias direction to substantially dissolve the conductive path;
c) each resistive storage element being biased in the reverse bias direction to be configured as a capacitor; and
d) the plurality of the resistive storage elements being configured as a corresponding plurality of capacitors, wherein the plurality of capacitors are connected in parallel.
8. The capacitive circuit of claim 7 , wherein the solid electrolyte comprises:
a) an injection barrier layer (IBL) coupled to the first electrode; and
b) a metal oxide coupled to the second electrode.
9. The capacitive circuit of claim 7 , wherein the first electrode comprises tungsten.
10. The capacitive circuit of claim 7 , further comprising a boundary cell that is outside of a functioning array of a plurality of resistive switching memory cells.
11. The capacitive circuit of claim 7 , wherein the resistive storage element comprises a conductive bridging random-access memory (CBRAM) storage element.
12. The capacitive circuit of claim 7 , wherein:
a) a first subset of the plurality of capacitors are connected in parallel;
b) a second subset of the plurality of capacitors are connected in parallel; and
c) the first and second subsets of capacitors are connected in series.
13. The capacitive circuit of claim 7 , further comprising a plurality of transistors, wherein each transistor is coupled between a corresponding one of the plurality of capacitors and ground.
14. The capacitive circuit of claim 13 , wherein each transistor is controllable by a capacitor enable control signal.
15. The capacitive circuit of claim 14 , further comprising:
a) a memory array having a designated register data portion, wherein the memory array comprises a plurality of resistive switching memory cells; and
b) a register configured to be programmed with data read from the designated register data portion.
16. The capacitive circuit of claim 15 , wherein the capacitor enable control signal is configured to be generated using the data from the register.