III-nitride transistor including a p-type depleting layer
A transistor includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor further includes a source, a drain, and a gate between the source and the drain, the gate being over the III-N layer structure. The p-type III-N layer includes a first portion that is at least partially in a device access region between the gate and the drain, and the first portion of the p-type III-N layer is electrically connected to the source and electrically isolated from the drain. When the transistor is biased in the off state, the p-type layer can cause channel charge in the device access region to deplete as the drain voltage increases, thereby leading to higher breakdown voltages.
1. A transistor, comprising:
a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer, wherein the III-N channel layer includes a 2DEG channel formed adjacent an interface between the III-N channel layer and the III-N barrier layer;
a source and a drain, each of which being directly connected to the III-N channel layer;
a gate between the source and the drain, the gate being over the III-N layer structure, wherein the p-type III-N layer includes a first portion that is disposed in a device access region between the gate and the drain; and
a field plate electrically connected to the source and to the first portion of the p-type III-N layer, wherein the first portion of the p-type III-N layer is electrically isolated from the drain.
2. The transistor of claim 1 , wherein a dopant concentration in the p-type III-N layer is such that an areal mobile charge density or a p-type doping density in the p-type III-N layer is in the range of 50-75% of an areal sheet charge density of mobile charge in the 2DEG channel.
3. The transistor of claim 2 , having a threshold voltage, wherein
mobile charge in the 2DEG channel in the access region between the gate and the drain is depleted while the gate is biased relative to the source at a voltage lower than the threshold voltage and the drain is biased above a minimum voltage relative to the source, but not depleted while the gate is biased relative to the source at a voltage lower than the threshold voltage and the drain is biased below the minimum voltage relative to the source, and
the minimum voltage is in a range of 20V to 100V.
4. The transistor of claim 1 , wherein
the p-type III-N layer further comprises a second portion disposed in a device access region between the source and the gate,
the transistor further comprises a recess extending through, and separating the first and second portions of, the p-type III-N layer, and
the gate is in the recess.
5. The transistor of claim 1 , wherein the III-N layer structure is oriented in an N-polar direction, and the gate is over an N-face of the III-N layer structure.
6. The transistor of claim 1 , wherein the p-type III-N layer includes a superlattice comprising alternating p-doped III-N layers and un-doped III-N layers.
7. A transistor, comprising:
a III-N channel layer;
a III-N barrier layer, wherein the III-N channel layer includes a 2DEG channel adjacent an interface between the III-N channel layer and the III-N barrier layer;
a source and a drain, each of which being directly connected to the III-N channel layer;
a gate between the source and the drain, the gate being over the 2DEG channel;
a p-type III-N layer disposed in a device access region between the gate and the drain; and
a field plate that is electrically connected to the source and to the p-type III-N layer, and is electrically isolated from the gate,
wherein the p-type III-N layer is electrically isolated from the drain, and
wherein a dopant concentration in the p-type III-N layer is such that an areal mobile charge density or a p-type doping density in the p-type III-N layer is in the range of 50-75% of an areal sheet charge density of mobile charge in the 2DEG channel.
8. The transistor of claim 7 , wherein
the p-type III-N layer has a portion disposed in a device access region between the source and the gate, and
the transistor further comprises a recess extending through the p-type III-N layer, such that the gate is in the recess.
9. The transistor of claim 7 , wherein
a III-N layer structure including the III-N channel layer, the III-N barrier layer and the p-type III-N layer is oriented in an N-polar direction, and
the gate is over an N-face of the III-N layer structure.
10. The transistor of claim 7 , wherein the p-type III-N layer includes a superlattice comprising alternating p-doped III-N layers and un-doped III-N layers.