Coreless package structure and method for manufacturing same

1. A method for manufacturing a coreless package structure comprising:

providing a supporting substrate comprising an etching resist layer and a first copper foil;

defining a groove in the first copper foil;

forming a plurality of contact pads on a surface of the first copper foil;

receiving a chip in the groove, the chip comprising a plurality of electrode pads on a side away from the etching resist layer;

forming a packaging layer on a side of the first copper foil, the packaging layer covering the chip, the contact pads, and the first copper foil exposed from the contact pads;

forming an insulating layer, a plurality of first conductive bumps, and a conductive pattern layer, the insulating layer adhered between the packaging layer and the conductive pattern layer, the conductive pattern layer electrically connected to the contact pads by the first conductive bumps, the conductive pattern layer electrically connected to the electrode pads by a plurality of second conductive bumps; and

removing the etching resist layer and the first copper foil, thereby, obtaining a coreless package structure;

wherein a method for forming the insulating layer, the first conductive bumps, the second conductive bumps, and the conductive pattern layer comprises:

laminating a first laminating substrate on a side of the packaging layer away from the supporting substrate, the first laminating substrate comprising an insulating layer and a second copper foil, the insulating layer adhered between the packaging layer and the second copper foil;

forming a plurality of first blind holes and a plurality of second blind holes defined by the second copper foil, the insulating layer, and the packaging layer by a laser drilling process, each of the contact pads corresponding to and exposed from one of the first blind holes, and each of the electrode pads corresponding to and exposed from one of the second blind holes;

forming the first conductive bumps, the second conductive bumps, and a conductive layer by an electroless plating process and then an electro plating process, each of the first conductive bumps being formed in one of the first blind holes, and corresponding to and electrically connected to one of the contact pads, each of the second conductive bumps being formed in one of the second blind holes, and corresponding to and electrically connected to one of the electrode pads, the conductive layer covering a portion of the second copper foil, the conductive layer being electrically connected to the first conductive bumps and the second conductive bumps; and

etching a portion of the second copper foil exposed from the conductive layer to obtain the conductive pattern layer.

2. The method of claim 1 , wherein the etching resist layer is made of nickel, and the etching resist layer and the first copper foil are removed by etching processes.

3. The method of claim 1 , wherein the supporting substrate further comprises a supporting layer, the supporting layer is located on a side of the etching resist layer away from the first copper foil, the supporting layer is removed before the etching resist layer and the first copper foil being removed.

4. The method of claim 1 , wherein the groove passes through the first copper foil, and a portion of the etching resist layer is exposed in the groove, a method for forming the groove comprises:

forming a photo resisting film on a surface of the first copper foil away from the etching resist layer, the first photo resisting film defining a through hole, a portion of the first copper foil being exposed from the through hole;

removing the portion of the first copper foil exposed from the through hole by an etching process, thereby, the groove being formed; and

removing the photo resisting film.

5. The method of claim 4 , wherein the chip is fixed on a surface of the etching resist layer exposed in the groove by an adhesive layer.

6. The method of claim 1 , wherein a method for forming the contact pads comprises:

forming a plating resisting film on a surface of the first copper foil away from the etching resist layer and a surface of the etching resist layer exposed in the groove, the plating resisting film defining a plurality of openings, portions of the first copper foil are exposed in the first openings;

forming the contact pads on surfaces of the first copper foil exposed in the first openings by an electroplating process; and

removing the plating resisting film.

7. The method of claim 1 , wherein the packaging layer is made of an epoxy, and is formed by a molding process.

8. The method of claim 1 , after forming the insulating layer, the first conductive bumps, and the conductive pattern layer, and before removing the etching resist layer and the first copper foil, further comprising forming at least one laminating structure on the surface of the conductive pattern layer away from the insulating layer.

9. A method for manufacturing a coreless package structure, comprising:

providing two supporting substrates comprising an etching resist layer and a first copper foil, a bonding sheet, and two copper sheets, the two copper sheets being bonded on either side of the bonding sheet, each of the two supporting substrates facing to one of the copper sheets and being adhered to the bonding sheets;

defining a groove in each one of the first copper foils;

forming a plurality of contact pads on a surface of each one of the first copper foils;

receiving a chip in each one of the grooves, the chip comprising a plurality of electrode pads on a side away from the etching resist layer;

forming a packaging layer on a side of each one of the first copper foils, the packaging layer covering the chip, the contact pads, and the first copper foil exposed from the contact pads;

forming an insulating layer, a plurality of first conductive bumps, and a conductive pattern layer on a surface of each one of the packaging layer, the insulating layer adhered between the packaging layer and the conductive pattern layer, the conductive pattern layer electrically connected to the contact pads by the first conductive bumps, the conductive pattern layer electrically connected to the electrode pads by a plurality of second conductive bumps; and

removing the bonding sheet, the two copper sheets, the etching resist layers and the first copper foils, thereby, obtaining two coreless package structures;

wherein a method for forming the insulating layer, the first conductive bumps, the second conductive bumps, and the conductive pattern layer comprises:

laminating a first laminating substrate on a side of the packaging layer away from the supporting substrate, the first laminating substrate comprising an insulating layer and a second copper foil, the insulating layer adhered between the packaging layer and the second copper foil;

forming a plurality of first blind holes and a plurality of second blind holes defined by the second copper foil, the insulating layer, and the packaging layer by a laser drilling process, each of the contact pads corresponding to and exposed from one of the first blind holes, and each of the electrode pads corresponding to and exposed from one of the second blind holes;

forming the first conductive bumps, the second conductive bumps, and a conductive layer by an electroless plating process and then an electro plating process, each of the first conductive bumps being formed in one of the first blind holes, and corresponding to and electrically connected to one of the contact pads, each of the second conductive bumps being formed in one of the second blind holes, and corresponding to and electrically connected to one of the electrode pads, the conductive layer covering a portion of the second copper foil, the conductive layer being electrically connected to the first conductive bumps and the second conductive bumps; and

etching a portion of the second copper foil exposed from the conductive layer to obtain the conductive pattern layer.

10. The method of claim 9 , wherein the etching resist layer is made of nickel, and the etching resist layer and the first copper foil are removed by etching processes.

11. The method of claim 9 , wherein the supporting substrate further comprises a supporting layer, the supporting layer is located on a side of the etching resist layer away from the first copper foil, the supporting layer is removed before the etching resist layer and the first copper foil being removed.

12. The method of claim 9 , wherein the groove passes through the first copper foil, and a portion of the etching resist layer is exposed in the groove, a method for forming the groove comprises:

forming a photo resisting film on a surface of the first copper foil away from the etching resist layer, the first photo resisting film defining a through hole, a portion of the first copper foil being exposed from the through hole;

removing the portion of the first copper foil exposed from the through hole by an etching process, thereby, the groove being formed; and

removing the photo resisting film.

13. The method of claim 12 , wherein the chip is fixed on a surface of the etching resist layer exposed in the groove by an adhesive layer.

14. The method of claim 9 , wherein a method for forming the contact pads comprises:

forming a plating resisting film on a surface of the first copper foil away from the etching resist layer and a surface of the etching resist layer exposed in the groove, the plating resisting film defining a plurality of openings, portions of the first copper foil are exposed in the first openings;

forming the contact pads on surfaces of the first copper foil exposed in the first openings by an electroplating process; and

removing the plating resisting film.

15. The method of claim 9 , wherein the packaging layer is made of an epoxy, and is formed by a molding process.

16. The method of claim 9 , after forming the insulating layer, the first conductive bumps, and the conductive pattern layer, and before removing the etching resist layer and the first copper foil, further comprising forming at least one laminating structure on the surface of the conductive pattern layer away from the insulating layer.