PSEUDO SELF ALIGNED RADHARD MOSFET AND PROCESS OF MANUFACTURE
A Vertical Power MOSFET (VDMOS) device with special features that enable the Power MOSFET or IGBT device to withstand harsh radiation environments and the process of making such a device is described. All implanted and diffused layers are “self aligned” to a “Sacrificial Poly” layer, which later on is removed, preparing the wafers for a “late gate” oxide to be grown. A starting material with graded doping profile in the epitaxial layer on the substrate is shown to increase the SEB capability of the Power MOSFET.
1 . A radhard VDMOS semiconductor device having a substrate of a first conductivity type, the device comprising:
a body region of a second conductivity type in the substrate;
a source region of the first conductivity type in the substrate;
a UIS region of the second conductivity type in the substrate;
a late gate oxide layer on an upper surface of the substrate overlying a channel region in the body region laterally adjacent the source region; and
a polysilicon layer on the late gate oxide layer overlapping the channel region;
wherein:
a first p-n junction between the substrate and the body region and a second p-n junction between the body region and the source region are tightly aligned,
the second p-n junction and a boundary between the source region and the UIS region are tightly aligned, and
at least one channel region formed between the first p-n junction and the second p-n junction;
wherein the body region and the UIS region are symmetrical around a vertical center axis through the body region.
2 . The radhard VDMOS semiconductor device of claim 1 wherein the late gate oxide is thermally grown on the upper surface of the substrate over the body, source and UIS regions and is substantially free from interface and oxide traps.
3 . The radhard VDMOS semiconductor device of claim 1 in which the substrate includes a wafer layer of a first doping concentration and an epitaxial layer having a second doping concentration less than the first doping concentration, and wherein the second doping concentration increases in a gradient proceeding from the upper surface to the wafer layer.
4 . The radhard VDMOS semiconductor device of claim 3 in which the source region includes two source regions spaced apart about a central body contact region, the device including a source contact contacting the two source regions and the central body region.