Hybrid printed circuit assembly with low density main core and embedded high density circuit regions

1. A method of making a high density circuit for a low density circuit comprising the steps of:

depositing at least a first liquid dielectric layer on the first surface of a first circuitry layer to include a plurality of first recesses;

processing selected surfaces of the first recesses to accept electro-less conductive plating deposition;

depositing conductive plating electro-lessly on the selected surfaces of the first recesses comprising a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer;

applying a plating resist to the high density circuit;

substantially filling the first recesses with a conductive material using electro-deposit plating; and

removing the plating resist.

2. The method of claim 1 comprising the steps of:

depositing at least a second liquid dielectric layer on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive structures;

processing selected surfaces of the second recesses to accept electro-less conductive plating deposition;

depositing a conductive material electro-lessly on the selected surfaces of the second recesses comprising a plurality of second conductive structures electrically coupled to, and extending generally perpendicular to, the first conductive structures;

applying a plating resist to the high density circuit;

substantially filling the second recesses with a conductive material using electro-deposit plating; and

removing the plating resist.

3. The method of claim 2 comprising planarizing the first dielectric layer and the first conductive structures before depositing the second dielectric layer.

4. The method of claim 2 comprising electrically coupling contact pads on an IC device to a plurality of the second conductive structures.

5. The method of claim 2 comprising the steps of:

locating a second circuitry layer on the second dielectric layer to electrically couple the second circuitry layer with a plurality of the second conductive structures; and

depositing a third dielectric layer on the second dielectric layer to include a plurality of third recesses generally aligned with a plurality of the second conductive structures.

6. The method of claim 5 comprising etching away portions of the second circuitry layer located in the third recesses to expose a plurality of the second conductive structures.

7. The method of claim 6 comprising the steps of:

plating a conductive material on surfaces of a plurality of the third recesses comprising a plurality of third conductive structure electrically coupled to, and extending parallel to the second conductive structures; and

electrically coupling contact pads on an IC device to a plurality of the third conductive structures, wherein the step of electrically coupling comprises one of a flip chip attachment directly to a plurality of third conductive structures, solder balls, or wire bonding.

8. The method of claim 1 comprising constructing the high density circuit directly on the low density circuit or as a discrete structure.

9. The method of claim 1 comprising the steps of:

forming the first circuitry layer on the low density circuit; and

constructing the high density circuit directly on the low density circuit.

10. The method of claim 1 comprising depositing a dielectric material in one or more of the recesses to surround one or more of the conductive structures.

11. The method of claim 1 comprising printing at least one electrical device on one of the dielectric layers and electrically coupling the electrical device to at least a portion of the circuitry layers.