Rinsing solution to prevent TiN pattern collapse
View Patent ↗The present invention is a new formulation and process for treating TiN semiconductor devices having a high aspect ratio structure formed thereon. The new composition is designed to be used in the chip making process between cleaning a wet etched memory device and its final rinse/drying process. It is intended to include the treatment in order to prevent collapse of the high aspect ratio TiN structure found on the semiconductor device.
1. A semiconductor pattern surface treatment composition for preventing collapse of high-aspect ratio TiN structures in a semiconductor memory device during fabrication comprising:
a) a solvent having predominantly polar characteristics, said solvent selected from the group of C 1 -C 6 alcohol or water; and
b) an anionic fluorosurfactant in an amount adequate to anchor to the surface of a TiN structure so that the contact angle of a rinse subsequently imposed thereon is sufficient to prevent collapse of said structure, wherein said anionic fluorosurfactant comprises a phosphorous-containing acid and a fluorinated alcohol.
2. The semiconductor pattern surface treatment composition according to claim 1 wherein said solvent is isopropanol or water.
3. The semiconductor pattern surface treatment composition according to claim 1 wherein said anionic fluorosurfactant further comprises at least one from the group of ammonium salts and ester-containing compounds.
4. The semiconductor pattern surface treatment composition according to claim 1 wherein said phosphorous-containing acid is selected from the group of phosphonic acid, phosphoric acid, hypophosphorous acid, tautomers, isomers, esters, salts, mixtures, and solutions thereof.
5. The semiconductor pattern surface treatment composition according to claim 1 wherein said fluorinated alcohol is a partially fluorinated alcohol selected from the group of perfluorooctylundecanol, trifluoroethanol, 4,4,5,5,5,-pentafluoro-1-penatanol, 4,4,4-trifluoro-1-butanol, alcohols of the formula HOC x H y F z (where x=1-20, and y+z=2x+1), and alcohols of the formula F(CF 2 CF 2 ) x CH 2 CH 2 OH, where x is 1 to 10.
6. The semiconductor pattern surface treatment composition according to claim 1 wherein said TiN structures have an aspect ratio of about less than 20:1.
7. The semiconductor pattern surface treatment composition according to claim 1 wherein said TiN structures have an aspect ratio of about 6:1 to about 20:1.
8. The semiconductor pattern surface treatment composition according to claim 1 wherein said contact angle of said isopropanol rinse on said TiN surface is at least about 15°.
9. The semiconductor pattern surface treatment composition according to claim 1 wherein said contact angle of said isopropanol rinse on said TiN surface is at least about 25°.
10. The semiconductor pattern surface treatment composition according to claim 1 wherein said contact angle of said isopropanol rinse on said TiN surface is at least about 40°.
11. The semiconductor pattern surface treatment composition according to claim 1 wherein said contact angle of said water rinse on said TiN surface is at least about 75°.
12. The semiconductor pattern surface treatment composition according to claim 1 wherein said contact angle of said water rinse on said TiN surface is at least about 100°.
13. The semiconductor pattern surface treatment composition according to claim 1 wherein said contact angle of said water rinse on said TiN surface is at least about 115°.
14. The semiconductor pattern surface treatment composition according to claim 1 wherein said anionic fluorosurfactant comprises from about 0.03% to about 15% by weight of the composition.
15. The semiconductor pattern surface treatment composition according to claim 1 wherein said anionic fluorosurfactant comprises from about 0.05% to about 10% by weight of the composition.