Sample-and-hold circuit and capacitive sensing device that includes the sample-and-hold circuit
View Patent ↗A sample-and-hold circuit is provided. The sample-and-hold circuit includes an input one or more dedicated capacitive elements, one or more parasitic capacitive elements connected to said one or more dedicated capacitive elements, an output, a group of switches, and a control unit. The control unit controls said switches so as to interconnect said input, said one or more dedicated capacitive elements, and said output in a cyclic manner in accordance with a sample-and-hold cycle.
1. A sample-and-hold circuit comprising:
an input;
one or more dedicated capacitive elements;
one or more parasitic capacitive elements connected to said one or more dedicated capacitive elements;
an output;
a group of switches; and
a control unit, wherein
said control unit is arranged to control said switches so as to interconnect said input, said one or more dedicated capacitive elements, and said output in a cyclic manner in accordance with a sample-and-hold cycle, and
the sample-and-hold cycle comprises, in chronological order,
an observation phase in which said one or more dedicated capacitive elements are disconnected from said output and connected to said input so as to adapt an electrical charge of said dedicated capacitive elements to an input voltage applied at said input,
a read-out phase in which said one or more dedicated capacitive elements are disconnected from said input and connected to said output so as to provide an output voltage in dependence on said electrical charge,
a sleep phase in which said one or more dedicated capacitive elements are disconnected from both said input and said output, said sleep phase involving a forward charge transfer between said one or more dedicated capacitive elements and said one or more parasitic capacitive elements, and
a restoration phase in which said one or more dedicated capacitive elements are disconnected from said input and connected to said output so as to cause a reverse charge transfer between said one or more dedicated capacitive elements and said one or more parasitic capacitive elements, said reverse charge transfer canceling said forward charge transfer at least partly.
2. The sample-and-hold circuit of claim 1 , wherein said control unit is arranged to set said switches into a read-out configuration in said read-out phase and into the same configuration in said restoration phase.
3. The sample-and-hold circuit of claim 1 , wherein said restoration phase is shorter than said observation phase.
4. The sample-and-hold circuit of claim 1 , wherein said cycle does not comprise any other phase after said restoration phase and before said observation phase.
5. The sample-and-hold circuit of claim 1 , wherein said sleep phase is a second sleep phase and said cycle comprises a first sleep phase after said observation phase and before said read-out phase.
6. The sample-and-hold circuit of claim 1 , comprising an operational amplifier arranged to output a reference voltage during said observation phase and to output said output voltage during said read-out phase.
7. The sample-and-hold circuit of claim 1 , wherein said observation phase comprises, in chronological order:
a first observation phase for sampling said input voltage; and
a second observation phase for inverting said input voltage and sampling the inverted input voltage.
8. The sample-and-hold circuit of claim 7 , wherein at least two of said dedicated capacitive elements are connected parallel after said observation phase and before said read-out phase so that charge balancing occurs to generate an output voltage-that corresponds to an average of said first input voltage and said inverted second input voltage.
9. The sample-and-hold circuit of claim 1 , comprising one or more resistive elements which in said observation phase are connected between said input and said one or more dedicated capacitive elements to form a low-pass filter.
10. The sample-and-hold circuit of claim 9 , wherein at least one of said one or more resistive elements has an adjustable resistance.
11. The sample-and-hold circuit of claim 1 , implemented as or in an integrated circuit.
12. The sample-and-hold circuit of claim 11 , comprising several layers stacked atop each other, said layers including at least a first layer and an adjoining second layer, said first layer comprising one or more metal shields, said second layer comprising said one or more dedicated capacitive elements at positions above or below one or more of said metal shields, said dedicated capacitive elements and said one or more metal shields together forming said parasitic capacitive elements.
13. A capacitive sensing device comprising a capacitive sensor and a sample-and-hold circuit as set forth in claim 1 , wherein said capacitive sensor is connected or connectable to said input of said sample-and-hold circuit.