Semiconductor structure including a ferroelectric transistor and method for the formation thereof
An illustrative semiconductor structure described herein includes a substrate including a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A logic transistor is provided at the logic transistor region. The logic transistor includes a gate dielectric and a gate electrode. An input/output transistor is provided at the input/output transistor region. The input/output transistor includes a gate dielectric and a gate electrode. The gate dielectric of the input/output transistor has a greater thickness than the gate dielectric of the logic transistor. A ferroelectric transistor is provided at the ferroelectric transistor region. The ferroelectric transistor includes a ferroelectric dielectric and a gate electrode. The ferroelectric dielectric is arranged between the ferroelectric transistor region and the gate electrode of the ferroelectric transistor.
1. A method, comprising:
providing a semiconductor structure comprising a logic transistor region, a ferroelectric transistor region and an input/output transistor region;
forming an input/output transistor dielectric over at least said input/output transistor region and said logic transistor region;
removing said input/output transistor dielectric from at least said logic transistor region;
after removing said input/output transistor dielectric from at least said logic transistor region, depositing a logic transistor dielectric over said semiconductor structure and depositing a first metal over said logic transistor dielectric;
removing said logic transistor dielectric and said first metal from said ferroelectric transistor region; and
forming a ferroelectric transistor dielectric over said ferroelectric transistor region.
2. The method of claim 1 , wherein said ferroelectric transistor dielectric is formed after the removal of said logic transistor dielectric and said first metal from said ferroelectric transistor region, the formation of said ferroelectric transistor dielectric comprising a deposition of said ferroelectric transistor dielectric over said semiconductor structure.
3. The method of 2 , further comprising depositing a second metal over said ferroelectric transistor dielectric.
4. The method of claim 3 , further comprising, after depositing said second metal, removing portions of said ferroelectric dielectric and said second metal over said logic transistor region and said input/output transistor region.
5. The method of claim 4 , wherein the removal of portions of said ferroelectric dielectric and said second metal over said logic transistor region and said input/output transistor region comprises performing an etch process adapted to selectively remove said ferroelectric dielectric relative to said first metal.
6. The method of claim 4 , further comprising:
before the deposition of said ferroelectric transistor dielectric over said semiconductor structure, depositing a protection layer over said semiconductor structure and removing a portion of said protection layer over said ferroelectric transistor region, said portions of said logic transistor dielectric and said first metal over said ferroelectric transistor region, and a portion of said input/output transistor dielectric over said ferroelectric transistor region.
7. The method of claim 6 , further comprising forming a first spacer adjacent a portion of said protection layer over said logic transistor region and a second spacer adjacent a portion of said protection layer over said input/output transistor region.
8. The method of claim 6 , further comprising removing portions of said protection layer over said logic transistor region and said input/output transistor region.
9. The method of claim 1 , wherein said ferroelectric transistor dielectric comprises a layer of silicon-doped hafnium dioxide.
10. The method of claim 9 , wherein said ferroelectric transistor dielectric further comprises a base layer comprising at least one of silicon dioxide and silicon nitride, said base layer being provided below said layer of silicon-doped hafnium dioxide.
11. The method of claim 1 , further comprising:
forming a first gate electrode over said logic transistor region;
forming a second gate electrode over said input/output transistor region; and
forming a third gate electrode over said ferroelectric transistor region.