Programmable impedance memory elements with laterally extending cell structure
View Patent ↗A memory device can include a plurality of memory elements formed over a substrate, including a plurality of first electrodes, each having a top surface and opposing side surfaces, a plurality of second electrodes formed on different vertical levels, each aligned with a corresponding first electrode in a lateral direction, and a memory material formed between each first electrode and an adjacent second electrode, the memory material being in contact with the opposing side surfaces of each first electrode and not in contact with the top surface of the first electrodes; wherein the memory material is electrically programmable between at least two different resistance states, and the lateral direction is parallel to a top surface of the substrate.
1. A memory device, comprising:
a plurality of memory elements formed over a substrate, including
a plurality of first electrodes, each having a top surface and opposing side surfaces,
a plurality of second electrodes formed on different vertical levels, each aligned with a corresponding first electrode in a lateral direction, and
a memory material formed between each first electrode and an adjacent second electrode, the memory material being in contact with the opposing side surfaces of each first electrode and not in contact with the top surface of the first electrodes; wherein
the memory material is electrically programmable between at least two different resistance states, and
the lateral direction is parallel to a top surface of the substrate.
2. The memory device of claim 1 , wherein:
the memory material comprises at least one ion conducting material.
3. The memory device of claim 1 , wherein:
the memory material is selected from the group of: a metal oxide and a chalcogenide.
4. The memory device of claim 1 , wherein:
the first electrodes comprise anodes that include an element that ion conducts in the memory material and the second electrodes comprise cathodes formed of a material that does not ion conduct in the memory material.
5. The memory device of claim 1 , wherein:
the first electrodes comprise a metal selected from the group of: silver and copper.
6. The memory device of claim 1 , wherein:
the second electrodes comprise anodes that include an element that ion conducts in the memory material and the first electrodes comprise cathodes formed of a material that does not ion conduct in the memory material.
7. The memory device of claim 1 , wherein:
each first electrode includes
a first portion that is bounded on opposing sides by the memory material, and
a connection portion that extends towards to contact the substrate.
8. A memory device, comprising:
a plurality of memory elements formed over a substrate, including
a plurality of first electrodes, each having a top surface and opposing side surfaces,
a plurality of second electrodes formed on different vertical levels, each aligned with a corresponding first electrode in a lateral direction, and
a memory material comprising an ion conductor formed between each first electrode and an adjacent second electrode, and not over the top surfaces of the first electrodes; wherein
the lateral direction is parallel to a top surface of the substrate.
9. The memory device of claim 8 , wherein:
the memory material is selected from the group of: a metal oxide and a chalcogenide.
10. The memory device of claim 8 , wherein:
the first electrodes comprise anodes that include an element that ion conducts in the memory material.
11. The memory device of claim 8 , wherein:
each memory element further includes an intervening layer formed between each first electrode and corresponding second electrode in addition to the memory material; wherein
the intervening layer is selected from the group of: an insulating layer and a conductive layer.
12. The memory device of claim 8 , wherein:
each second electrode is common to a plurality of different memory elements.
13. The memory device of claim 8 , further including:
a plurality of access devices formed in the substrate; and
each first electrode is electrically connected to one of the access devices.
14. The memory device of claim 13 , wherein:
the access devices are selected from the group of: transistors, diodes and thyristors.
15. A memory device, comprising:
a plurality of first electrodes each having opposing side surfaces; and
a plurality of second electrodes, each having a side surface aligned in a lateral direction with at least one opposing side surface of a corresponding first electrode and separated therefrom by a memory material, the second electrodes being disposed at different vertical levels over a substrate; wherein
pairs of first and second electrodes each form a memory element programmable between different impedance states by electrically programming the memory material between different impedance values.
16. The memory device of claim 15 , wherein:
the memory material comprises an ion conductor; and
the first electrodes comprise a metal that is ion conductible in the memory material.
17. The memory device of claim 15 , wherein:
top surfaces of some of the first electrodes are coplanar with top surfaces of some of the second electrodes.
18. The memory device of claim 15 , wherein:
each second electrode is common to a plurality of different memory elements.
19. The memory device of claim 15 , wherein:
the first electrodes comprise a metal selected from the group of: silver and copper.
20. The memory device of claim 15 , wherein:
the memory material comprises a material selected from the group of: a metal oxide and a chalcogenide.