Semiconductor component and method of manufacture
In accordance with an embodiment, a method for manufacturing a semiconductor component includes forming a first trench through a plurality of layers of compound semiconductor material. An insulating material is formed on first and second sidewalls of the first trench and first and second sidewalls of the second trench and a trench fill material is formed in the first and second trenches. In accordance with another embodiment, the semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.
1. A method for manufacturing a semiconductor component, comprising:
providing a semiconductor material having a surface;
forming a nucleation layer on the semiconductor material;
forming a first portion of a buffer layer on the nucleation layer;
forming an electric field stop layer on the first portion of the buffer layer;
forming a second portion of the buffer layer on the electric field stop layer;
forming a plurality of trenches, wherein each trench extends through the second portion of the buffer layer, through the electric field stop layer, through the first portion of the buffer layer, and into the semiconductor material, and wherein each trench has a floor and opposing sidewalls;
forming a layer of insulating material on at least the opposing sidewalls of a first trench of the plurality of trenches and on the opposing sidewalls of a second trench of the plurality of trenches; and
forming a trench fill material in the first trench and in the second trench,
wherein the first portion of the buffer layer comprises graded superlattice and a doping concentration of the field stop layer is higher than a doping concentration of the second portion of the buffer layer.
2. The method of claim 1 , further including forming the electric field stop layer to be in contact with the first portion of the buffer layer and forming the second portion of the buffer layer to be in contact with the electric field stop layer.
3. The method of claim 1 , wherein forming the layer of insulating material on the opposing sidewalls of the first trench and on the opposing sidewalls of the second trench includes forming one of aluminum nitride or silicon nitride on the opposing sidewalls of the first trench and on the opposing sidewalls of the second trench.
4. The method of claim 3 , wherein forming the trench fill material in the first trench and in the second trench includes forming one of an electrically conductive material or an electrically insulating material in the first trench and in the second trench.
5. The method of claim 4 , further including forming the layer of insulating material on the floor of the second trench of the plurality of trenches, wherein forming the trench fill material in the first trench and in the second trench includes forming the electrically conductive material in the first trench to contact the semiconductor material, wherein the electrically conductive material in the second trench is electrically isolated from the semiconductor material.
6. The method of claim 1 , further including forming the layer of insulating material on the floor of the first trench and on the floor of the second trench.
7. The method of claim 6 , wherein forming the layer of insulating material on the floors and on the opposing sidewalls of the first trench and the second trench includes forming one of aluminum nitride or silicon nitride on the floors and on the opposing sidewalls of the first trench and the second trench.
8. The method of claim 1 , further including forming a channel layer on the second portion of the buffer layer, forming a strained layer on the channel layer, forming a control electrode and first and second current carrying electrodes over the strained layer and forming an electrical interconnect between one of the first current carrying electrode or the second current carrying electrode and the trench fill material in the first trench.
9. A method for manufacturing a semiconductor component, comprising:
providing a semiconductor material;
forming a nucleation layer on the semiconductor material;
forming a first portion of a buffer layer on the nucleation layer;
forming an electric field stop layer on the first portion of the buffer layer;
forming a second portion of the buffer layer on the electric field stop layer;
forming a channel layer on the second portion of the buffer layer;
forming a strained layer on the channel layer;
forming a first isolation structure extending through the strained layer, into the channel layer, through the second portion of the buffer layer, the electric field stop layer, the first portion of the buffer layer, and the nucleation layer;
forming a second isolation structure extending through the strained layer, into the channel layer, through the second portion of the buffer layer, the electric field stop layer, the first portion of the buffer layer, and the nucleation layer; and
forming a control electrode and a first current carrying electrode over the portion of the strained layer that is between the first isolation structure and the second isolation structure,
wherein the first portion of the buffer layer comprises graded superlattice and a doping concentration of the field stop layer is higher than a doping concentration of the second portion of the buffer layer.
10. The method of claim 9 , wherein forming the first portion of the buffer layer includes forming the first portion of the buffer layer using a first reactant composition, forming the electric field stop layer includes using a second reactant composition, and forming the second portion of the buffer layer using a third reactant composition.
11. The method of claim 9 , further including forming the electric field stop layer between and in contact with the first portion of the buffer layer and the second portion of the buffer layer.
12. The method of claim 1 , further including forming a channel layer on the second portion of the buffer layer.