IP Library Granted Patent US 9,294,763
Granted Patent B2
US 9,294,763 · App. 14/456,959 · Granted Mar 22, 2016

Self test of image signal chain while running in streaming mode

Inventors: Johannes Solhusvik (Haslum, NO); Tore Martinussen (Strommen, NO)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H04N17/002H04N5/378
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Quick Facts
Patent No.
US 9,294,763
App. No.
14/456,959
Granted
Mar 22, 2016
Kind
B2
Abstract

An imager including a self test mode. The imager includes a pixel array for providing multiple pixel output signals via multiple columns; and a test switch for (a) receiving a test signal from a test generator and (b) disconnecting a pixel output signal from a column of the pixel array. The test switch provides the test signal to the column of the pixel array. The test signal includes a test voltage that replaces the pixel output signal. The test signal is digitized by an analog-to-digital converter (ADC) and provided to a processor. The processor compares the digitized test signal to an expected pixel output signal. The processor also interpolates the output signal from a corresponding pixel using adjacent pixels, when the test switch disconnects the pixel output signal from the column of the pixel array.

Claims (33)

1. An imager including a self test mode comprising: a pixel array for providing pixel output signals, a plurality of analog-to-digital converters (ADCs) for converting the pixel output signals into pixel digital data, a digital processor for processing the pixel digital data, and a multiplexer for receiving a test signal and the pixel digital data, wherein the multiplexer provides the test signal to the digital processor for testing the imager.

2. The imager of claim 1 wherein the test signal includes a row of pixel values.

3. The imager of claim 1 wherein the test signal includes a full frame test pattern.

4. The imager of claim 1 wherein the test signal is provided by the multiplexer to the digital processor during a vertical blanking period of the imager.

5. The imager of claim 1 wherein the test signal includes multiple values for each pixel in at least one row of pixels, and the multiple values are provided to the multiplexer during multiple vertical blanking periods of the imager.

6. A self-testing imaging system comprising:

a plurality of pixels that generate pixel output values;

a plurality of analog-to-digital converters that convert the pixel output values to digital pixel values;

a multiplexer that receives the digital pixel values and a test stimulus and that multiplexes the digital pixel values with the test stimulus to generate test data; and

a processor that receives the test data and compares the test data with predetermined test data.

7. The self-testing imaging system of claim 6 , wherein the test stimulus comprises digital test stimulus values corresponding to a selected row of pixels in the plurality of pixels.

8. The self-testing imaging system of claim 7 , wherein the digital test stimulus values are multiplexed with the digital pixel values generated by the selected row of pixels to generate the test data.

9. A method of testing an imaging system, comprising:

generating pixel output values with a pixel array;

converting the pixel output values to digital pixel data with analog-to-digital converter circuitry;

receiving the digital pixel data and test values at a multiplexer;

with the multiplexer, multiplexing the digital pixel data and the test values to produce test data; and

comparing the test data to predetermined test data.

10. The method defined in claim 9 , wherein the pixel output values are generated by a row of pixels in the pixel array.

11. The method defined in claim 9 , wherein the test values are received at the multiplexer during a vertical blanking time of the imaging system.

12. The method defined in claim 10 , wherein the test values correspond to the row of pixels in the array.

13. The method defined in claim 10 , further comprising:

generating test signals with a test voltage generator; and

receiving the test signals at the analog-to-digital converter circuitry.

14. The method defined in claim 13 , further comprising:

with the analog-to-digital converter circuitry, digitizing the test signals to generate the test values that are received at the multiplexer.

15. The method defined in claim 11 , wherein the test values are received from the analog-to-digital converter circuitry.

16. The self-testing imaging system of claim 7 , further comprising:

a test voltage generator that provides test voltages to the plurality of analog-to-digital converters.

17. The self-testing imaging system of claim 16 , wherein the plurality of analog-to-digital converters convert the test voltages to the digital test stimulus values that are received at the multiplexer.

18. The self-testing imaging system of claim 16 , wherein the test voltage generator provides the test voltages are to the analog-to-digital converters during a vertical blanking time of the imaging system.

19. The self-testing imaging system of claim 18 , wherein a ground voltage is provided to the analog-to-digital converters during the vertical blanking time of the imaging system.

20. The self-testing imaging system of claim 18 , wherein the test voltage generator provides one of the test voltages and an additional test voltage to at least one of the analog-to-digital converters during the vertical blanking time of the imaging system.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2015
From: APTINA IMAGING CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 036555/0382 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2015
From: SOLHUSVIK, JOHANNES; MARTINUSSEN, TORE
To: APTINA IMAGING CORPORATION
Reel/Frame 035044/0198 →
Continuity (2)
Division 13248120 · Sep 29, 2011
Related Publication 20140347496A1 · Nov 27, 2014