True random number generator with repeatedly activated oscillator
A true random number generator (RNG) has one or more oscillators and an output register for storing a random number output. Each of the oscillators is activated, successively, in a free-running oscillation phase, and a capture phase during which the oscillator is quiescent. The output register latches during the capture phase of each oscillator an end state of that oscillator at or close to the end of its oscillation phase. The random number output is derived from the latched end states.
1. A true random number generator (TRNG), comprising:
two or more oscillators; and
an output register connected to the two or more oscillators for storing a random number output by the oscillators,
wherein each of the oscillators is activated, successively, with a free-running oscillation phase and a capture phase during which the oscillator is quiescent, and
wherein the output register latches during the capture phase of each oscillator an end state of that oscillator at or close to the end of its oscillation phase, and a random number is derived from the latched end states.
2. The TRNG of claim 1 , wherein each of the two or more oscillators is a ring oscillator having an odd number of inverters connected in series between an oscillator input and an oscillator output, and a feedback loop from the oscillator output to the oscillator input.
3. The TRNG of claim 2 , wherein the inverters are tri-state inverters having a high impedance during the capture phase.
4. The TRNG of claim 1 , further comprising:
a signal processor controlled by a control signal for latching the end states of the two or more oscillators and applying selected end states to the output register, and
wherein the control signal controls the oscillation phases and the capture phases of the two or more oscillators.
5. The TRNG of claim 4 , wherein the output register is a serial-input register, and the signal processor applies the latched end states of the two or more oscillators to the output register.
6. The TRNG of claim 5 , wherein the two or more oscillators comprise a pair of oscillators, and the signal processor applies the latched end states of the oscillators of the pair alternately to the serial-input register.
7. The TRNG of claim 4 , wherein the two or more oscillators comprise a plurality of oscillators, the output register comprises a parallel input register, and the signal processor applies the latched end states of the oscillators in parallel to the inputs of the parallel-input register.
8. The TRNG of claim 7 , wherein the plurality of oscillators comprises a plurality of pairs of oscillators, wherein the signal processor applies the latched end states of the oscillators of each pair alternately to the respective parallel inputs of the output register.
9. A true random number generator (TRNG), comprising:
at least one pair of oscillators; and
an output register for storing a random number output,
wherein each oscillator of the pair is activated in, successively, a free-running oscillation phase and a capture phase during which the oscillator is quiescent, and
wherein the output register latches during the capture phase of each oscillator of the pair in succession an end state of that oscillator at or close to the end of its oscillation phase, and derives the random number output from the latched end states.
10. The TRNG of claim 9 , wherein the oscillators are ring oscillators having an odd number of inverters connected in series between an oscillator input and an oscillator output, and a feedback loop from the oscillator output to the oscillator input.
11. The TRNG of claim 10 , wherein the inverters are tri-state inverters presenting high impedance during the capture phase.
12. The TRNG of claim 9 , further comprising:
a signal processor connected between the oscillators and the output register, wherein a control signal controls the oscillation phases and the capture phases of the oscillators, and wherein the signal processor is controlled by the control signal for latching the end states of the oscillators and applying selected end states to the output register.
13. The TRNG of claim 12 , wherein the output register is a serial-input register, and the signal processor applies the latched end states of the oscillators of the pair alternately to the serial-input register.
14. The TRNG of claim 12 , wherein the at least one pair of oscillators comprises a plurality of pairs of oscillators, wherein the output register is a parallel-input register having a plurality of inputs, and the signal processor applies the latched end states of the oscillators in parallel to the inputs of the parallel-input register.
15. A method of generating a true random number (TRN) comprising:
Activating two or more oscillators in, successively, a free-running oscillation phase, and a capture phase during which the oscillators are quiescent; and
latching in an output register during the capture phase of each oscillator an end state of that oscillator at or close to the end of its oscillation phase, and deriving a TRN from the latched end states.
16. The method of claim 15 , wherein each oscillator is a ring oscillator having an odd number of inverters connected in series between an oscillator input and an oscillator output, and a feedback loop from the oscillator output to the oscillator input.
17. The method of claim 16 , wherein the inverters are tri-state inverters presenting high impedance during the capture phase.
18. The method of claim 15 , wherein a control signal controls the oscillation phases and the capture phases of each oscillator, and wherein a signal processor controlled by the control signal latches the end states of the oscillators and applies selected end states to the output register.
19. The method of claim 18 , wherein the two or more oscillators comprises at least one pair of the oscillators, wherein the output register is a serial-input register, and wherein the signal processor applies the latched end states of the oscillators of the pair alternately to the serial-input register.
20. The method of claim 18 , wherein the output register is a parallel-input register having a plurality of inputs, and wherein the signal processor applies the latched end states of the two or more oscillators in parallel to the inputs of the parallel-input register.