IP Library Granted Patent US 9,129,839
Granted Patent B2
US 9,129,839 · App. 14/477,212 · Granted Sep 8, 2015

Method of fabricating a FinFET device

Inventors: Ming-Feng Shieh (Tainan County, TW); Chen-Yu Chen (Taipei, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L27/0886H01L21/28123H01L21/3086H01L21/76H01L21/823431H01L29/06H01L29/0649H01L29/6681
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Quick Facts
Patent No.
US 9,129,839
App. No.
14/477,212
Granted
Sep 8, 2015
Kind
B2
Abstract

A semiconductor device includes a substrate and a plurality of fin structures. A first fin structure and a second fin structure are spaced at a distance D 1 . A first dummy fin structure is adjacent to the first fin structure, and a second dummy fin structure is adjacent to the second fin structure. The device further includes an isolation layer over the substrate and the first and second dummy fin structures, and surrounding the first and second fin structures. The fin structures are arranged such that a distance D 2 between the first fin structure and the first dummy fin structure is greater than the distance D 1.

Claims (47)

1. A semiconductor device, comprising:

a substrate;

a first fin structure and a second fin structure spaced at a distance D 1 ;

a first dummy fin structure adjacent to the first fin structure without any intervening fin structure, and a second dummy fin structure adjacent to the second fin structure without any intervening fin structure; and

an isolation layer over the substrate and the first and second dummy fin structures, and surrounding the first and second fin structures;

wherein a distance D 2 between the first fin structure and the first dummy fin structure is greater than the distance D 1 .

2. The device of claim 1 , wherein the substrate includes silicon, and wherein the first and second dummy fin structures include silicon.

3. A semiconductor device, comprising:

a substrate;

a first fin structure and a second fin structure spaced at a distance D 1 ;

a first dummy fin structure adjacent to the first fin structure, and a second dummy fin structure adjacent to the second fin structure; and

an isolation layer over the substrate and the first and second dummy fin structures, and surrounding the first and second fin structures;

wherein a distance D 2 between the first fin structure and the first dummy fin structure is greater than the distance D 1 , and

wherein the first and second fin structures include amorphous carbon and silicon oxynitride.

4. A semiconductor device, comprising:

a substrate;

a first fin structure and a second fin structure spaced;

a first dummy fin structure adjacent to the first fin structure without any intervening fin structure, and a second dummy fin structure adjacent to the second fin structure without any intervening fin structure; and

an isolation layer over the substrate and the first and second dummy fin structures, and surrounding the first and second fin structures;

wherein the first and second fin structures are spaced at a distance D 1 , the first fin structure and the first dummy fin structure are spaced at a distance D 2 , and D 2 is greater than two times of D 1 .

5. The device of claim 4 , wherein the isolation structure buries the dummy fins.

6. The device of claim 4 , wherein the substrate includes silicon, and wherein the first and second dummy fin structures include silicon.

7. The device of claim 4 , wherein the substrate includes layers of silicon, amorphous carbon (APF), and silicon oxynitride.

8. A semiconductor device, comprising:

a substrate;

a first fin structure and a second fin structure spaced;

a first dummy fin structure adjacent to the first fin structure, and a second dummy fin structure adjacent to the second fin structure; and

an isolation layer over the substrate and the first and second dummy fin structures, and surrounding the first and second fin structures;

wherein the first and second fin structures have been modified by a cut process, and

wherein the fin structures include layers of silicon, amorphous carbon (APF), and a capping layer.

9. The device of claim 8 , wherein the capping layer is silicon oxynitride.

10. A semiconductor device, comprising:

a substrate;

a first fin structure and a second fin structure;

a first dummy fin structure adjacent to the first fin structure, and a second dummy fin structure adjacent to the second fin structure; and

an isolation layer over the substrate and the first and second dummy fin structures, and surrounding the first and second fin structures;

wherein the first and second fin structures include amorphous carbon and silicon oxynitride.

11. The device of claim 10 , wherein a distance between the first fin structure and the first dummy fin structure is greater than a distance between the first fin structure and the second fin structure.

12. The device of claim 10 , wherein the substrate includes silicon, and wherein the first and second dummy fin structures include silicon.

13. The device of claim 10 , wherein the first and second fin structures have been modified by a cut process.

14. The device of claim 10 , wherein the substrate includes a plurality of layers.

15. The device of claim 14 , wherein the plurality of layers include silicon oxide, silicon nitride, silicon oxynitride layer, or combination thereof.

16. The device of claim 11 , wherein the isolation layer includes silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

17. The device of claim 16 , wherein the isolation structure is formed using a deposition process.

18. The device of claim 17 , wherein the isolation structure has a planarized surface.

19. The device of claim 11 , wherein the first and second dummy fin structures have been modified by a cut process.

20. The device of claim 11 , wherein the substrate includes silicon germanium.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2014
From: SHIEH, MING-FENG; CHEN, CHEN-YU
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 033669/0848 →
Continuity (3)
Division 13871644 · Apr 26, 2013
Provisional Application 61777083 · Mar 12, 2013
Related Publication 20140367785A1 · Dec 18, 2014