IP Library Granted Patent US 9,232,156
Granted Patent B1
US 9,232,156 · App. 14/492,573 · Granted Jan 5, 2016

Video processing device and method

Inventors: Michael Andreas Staudenmaier (Munich, DE); Stephan Herrmann (Markt Schwaben, DE); Robert Cristian Krutsch (Munich, DE)
Assignee: Freescale Semiconductor, Inc.
H04N5/265
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Quick Facts
Patent No.
US 9,232,156
App. No.
14/492,573
Granted
Jan 5, 2016
Kind
B1
Abstract

A video processing device for generating an output video stream on the basis of two or more concurrent input video streams and a method thereof are described. Each input video stream comprises a sequence of input images. The output video stream comprises a sequence of output images. The video processing device generates each output image by merging a respective set of input images. The set of input images comprises one input image from each input video stream. The video processing device merges the input images in a series of merging rounds. Each merging round comprises forming an output tile by merging a set of input tiles, and writing the output tile to an output memory unit. The set of input tiles comprises one input tile from each input image of the respective set of input images. The output tiles written to the output memory unit represent the output image.

Claims (23)

1. A video processing device for generating an output video stream on the basis of two or more concurrent input video streams, wherein each of the input video streams comprises a sequence of input images, the output video stream comprises a sequence of output images, and the video processing device is arranged to generate each of said output images by merging a respective set of input images, wherein the set of input images comprises one input image from each of said input video streams and wherein the video processing device is arranged to merge the set of input images in a series of two or more merging rounds, wherein each merging round comprises:

forming an output tile by merging a set of input tiles, wherein the set of input tiles comprises one input tile from each input image of the respective set of input images, and

writing the output tile to an output memory unit, wherein the output tiles written to the output memory unit in said series of merging rounds represent the output image;

wherein the video processing device comprises a tile buffer and a processing unit and is arranged to merge the set of input tiles by:

providing at least a part of input tile data in the tile buffer, the input tile data representing the set of input tiles; and

operating the processing unit to retrieve input tile data from the tile buffer required for computing at least a part of the output tile and to compute the output tile on the basis of the retrieved input tile data;

and wherein the processing unit is arranged to stop computing the output tile in response to detecting that required input tile data is not present in the tile buffer and to resume computing the output tile in response to retrieving the required input tile data from the tile buffer.

2. The video processing device of claim 1 , wherein the processing unit has an processing capacity, which is sufficiently high to enable the processing unit to make up for periods during which it waits for the required input tile data to arrive in the tile buffer.

3. The video processing device of claim 1 , wherein the input tile data represents only the set of input tiles or a portion thereof, and not the set of input images.

4. The video processing device of claim 1 , comprising a random access memory unit, which comprises the tile buffer.

5. The video processing device of claim 1 , wherein the tile buffer is a first-in first-out buffer.

6. The video processing device of claim 1 , wherein each of the input video streams has tile definitions associated with it, which are the same for each image of the respective input video stream and which define the shape and position of each tile of the respective image.

7. The video processing device of claim 1 , wherein the input tiles in the set of input tiles are band-shaped.

8. The video processing device of claim 1 , connected or connectable to two or more video sources so as to receive each of said video streams from a respective one of the video sources.

9. The video processing device of claim 1 , wherein each output image of the output video stream represents a panoramic view, a surround view, or a bird's eye view.

10. The video processing device of claim 1 , located on a single chip.

11. A method of generating an output video stream on the basis of two or more concurrent input video streams, wherein each of the input video streams comprises a sequence of input images, the output video stream comprises a sequence of output images, and the method comprises, for each of said output images:

generating the output image by merging a set of input images, wherein the set of input images comprises one input image from each of said input video streams and wherein said operation of merging the set of input images comprises a series of two or more merging rounds, wherein each round comprises:

forming an output tile by merging a set of input tiles, wherein the set of input tiles comprises one input tile from each input image of said set of input images, wherein merging the set of input tiles comprises:

providing at least a part of input tile data in a tile buffer, the input tile data representing the set of input tiles; and

operating a processing unit to retrieve the at least part of the input tile data from the tile buffer and to compute the output tile on the basis of the retrieved input tile data, comprising:

stopping computing the output tile in response to detecting that required input tile data is not present in the tile buffer and

resuming computing the output tile in response to retrieving the required input tile data from the tile buffer.

Assignments (14)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0460 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0502 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0921 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0351 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0370 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034153/0027 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2014
From: STAUDENMAIER, MICHAEL ANDREAS; HERRMANN, STEPHAN; KRUTSCH, ROBERT CRISTIAN
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 033787/0867 →