IP Library Granted Patent US 9,281,335
Granted Patent B2
US 9,281,335 · App. 14/494,215 · Granted Mar 8, 2016

Alignment marks and alignment methods for aligning backside components to frontside components in integrated circuits

Inventors: Gianluca Testa (Avezzano, IT); Giovanni De Amicis (L'Aquila, IT)
Assignee: Semiconductor Components Industries, LLC
H01L27/14634H01L23/544H01L27/1464H01L27/14621H01L27/14627H01L27/14636H01L27/14687H01L2225/06593H01L2924/0002
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Quick Facts
Patent No.
US 9,281,335
App. No.
14/494,215
Granted
Mar 8, 2016
Kind
B2
Abstract

An imaging system may include an imager integrated circuit with frontside components such as imaging pixels and backside components such as color filters and microlenses. The imager integrated circuit may be mounted to a carrier wafer with alignment marks. Bonding marks on the carrier wafer and the imager integrated circuit may be used to align the carrier wafer accurately to the imager integrated circuit. The alignment marks on the carrier wafer may be read, by fabrication equipment, to align backside components of the imager integrated circuit, such as color filters and microlenses, with backside components of the imager integrated circuit, such as photodiodes.

Claims (44)

1. A system, comprising:

a central processing unit;

memory;

input-output circuitry; and

an imaging device, comprising:

a device substrate having a first side and a second side;

a plurality of semiconductor components located on the first side of the device substrate;

a carrier substrate having a first side mounted to the first side of the device substrate and having alignment marks on a second side; and

at least one component on the second side of the device substrate, wherein the at least one component is formed in alignment with the semiconductor components located on the first side of the device substrate and the alignment marks on the second side of the carrier substrate.

2. The system defined in claim 1 , wherein the plurality of semiconductor components comprises an array of image sensor pixels.

3. The system defined in claim 2 , wherein the plurality of semiconductor components comprises reset transistors, transfer transistors, floating diffusion storage nodes, and source-follower transistors.

4. The system defined in claim 1 , wherein the imaging device further comprises:

a plurality of layers of metal interconnects and vias electrically coupled to the semiconductor components located on the first side of the device substrate.

5. The system defined in claim 4 , wherein the imaging device further comprises:

an oxide bonding layer interposed between the device substrate and the carrier substrate.

6. The system defined in claim 1 , wherein the device substrate forms part of an integrated circuit die, and wherein the integrated circuit die further includes bonding marks formed over the first side of the device substrate.

7. The system defined in claim 6 , wherein the carrier substrate further comprises bonding marks formed at the first side of the carrier substrate, and wherein the bonding marks on the carrier substrate are aligned to the bonding marks in the integrated circuit die.

8. An image sensor, comprising:

a device substrate having a front side and a back side;

a photosensitive element formed in the front side of the device substrate;

a carrier substrate having a front side that faces the front side of the device substrate and a back side at which alignment marks are formed; and

at least one component formed on the back side of the device substrate, wherein the at least one component is formed in alignment with the photosensitive element and the alignment marks on the back side of the carrier substrate.

9. The image sensor defined in claim 8 , further comprising:

a bonding layer coupled between the device substrate and the carrier substrate.

10. The image sensor defined in claim 8 , wherein the at least one component comprises a color filter.

11. The image sensor defined in claim 8 , wherein the at least one component comprises a microlens.

12. The image sensor defined in claim 8 , further comprising:

additional alignment marks formed in the front side of the device substrate.

13. The image sensor defined in claim 8 , further comprising:

alternating layers of conductive vias and conductive lines formed on the front side of the device substrate.

14. The image sensor defined in claim 13 , further comprising:

first bonding marks formed on the alternating layers; and

second bonding marks formed in the front side of the carrier substrate, wherein the second bonding marks are aligned to the first bonding marks.

15. Circuitry, comprising:

an integrated circuit die having a front side and a back side, wherein the integrated circuit die includes first bonding marks formed on the front side of the integrated circuit die; and

a carrier substrate having a front side and a back side, wherein the carrier substrate is bonded to integrated circuit die, and wherein the carrier substrate includes second bonding marks that are formed in the front side of the carrier substrate and that are aligned to the first bonding marks.

16. The circuitry defined in claim 15 , wherein the integrated circuit die includes a plurality of photosensitive elements formed at the front side of the integrated circuit.

17. The circuitry defined in claim 15 , wherein the front side of the carrier substrate faces the front side of the integrated circuit die.

18. The circuitry defined in claim 15 , further comprising:

alignment marks formed on the back side of the carrier substrate; and

image sensor components that are formed on the back side of the integrated circuit and that are formed in alignment with the alignment marks.

19. The circuitry defined in claim 18 , further comprising:

additional alignment marks formed in the integrated circuit die.

20. The circuitry defined in claim 18 , wherein the image sensor components comprises components selected from the group consisting of color filter elements and microlenses.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2014
From: APTINA IMAGING CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034673/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2014
From: TESTA, GIANLUCA; DE AMICIS, GIOVANNI
To: MICRON TECHNOLOGY, INC.
Reel/Frame 034490/0564 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2014
From: MICRON TECHNOLOGY, INC.
To: APTINA IMAGING CORPORATION
Reel/Frame 034490/0631 →
Continuity (3)
Continuation 13540905 · Jul 3, 2012
Provisional Application 61505492 · Jul 7, 2011
Related Publication 20150102445A1 · Apr 16, 2015