IP Library Patent Application 14494438
Patent Application
App. No. 14/494,438

PACKET PROTOCOL PROCESSING WITH PRECISION TIMING PROTOCOL SUPPORT

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Quick Facts
Patent No.
US None
App. No.
14/494,438
Abstract

Device and methods determine timing parameters and associated timing actions from timing messages in communication packets. The timing messages may be encapsulated with plurality of communication protocols. An example timing message may be an IEEE 1588 timing message encapsulated in an Internet protocol packet encapsulated in an Ethernet protocol packet. The protocols are matched in classifier blocks by comparing portions of the packet to bit values or ranges of values. Operation of other than the first classifier block depends on results of matching in the preceding block by using offset values passed between blocks that indicate starting points for the matching. The final classifier block matches values in timing messages to identify timing parameters and associated timing actions in the message.

Claims (30)

1 .- 14 . (canceled)

15 . A method of determining how to adjust a time stamp, comprising:

providing a packet to a plurality of sequentially arranged comparison blocks,

sequentially performing a comparison of bits of the packet with preidentified bits by at least some of the sequentially arranged comparison blocks;

providing, by each of the comparison blocks other than an ultimate comparison block, an offset indicator to a subsequent comparison block of the plurality of sequentially arranged comparison blocks; and

determining, by the ultimate comparison block, an action to take with respect to the time stamp.

16 . The method of claim 15 , wherein the bits of the packet other than the bits for the first comparison are selected based on the offset indicator.

17 . The method of claim 16 , further comprising modifying the time stamp based on the determined action.

18 . The method of claim 16 , further comprising forming a signature identifying the packet by selecting portions of the packet by at least one of the comparison blocks.

19 . Circuitry in a physical layer (PHY) device for at least determining a location of a time stamp, comprising:

start of frame circuitry for determining a start of a frame signal; and

alignment circuitry for aligning data of a frame in accordance with the start of frame signal;

at least one set of classifier blocks, each of the classifier blocks configured to compare bits of the frame with preidentified bits indicated by an offset for at least the classifier blocks other than an initial one of the classifier blocks of the set of classifier blocks, with the last of the classifier blocks indicating a time stamp location.

20 . The circuitry of claim 19 , wherein at least some of the classifier clocks are configured to provide a signal indicative of order of operation of the classifier blocks.

21 . The circuitry of claim 19 , further comprising a signature block configured to produce a signature of the frame from signature components, and

where at least one of the classifier blocks is further configured to select preidentified portions of the frame as for the signature components.

22 . The circuitry of claim 19 , wherein the at least one set of classifier blocks comprises a plurality of sets of classifier blocks.

23 . The circuitry of claim 22 , wherein the plurality of sets of classifier blocks are configured to substantially simultaneously perform the comparisons.

24 . The circuitry of claim 22 , further comprising a plurality of ports and circuitry selectively coupling the sets of classifier blocks to the parts.

25 . A method of extracting information from a packet using a plurality of stages, comprising:

receiving a packet;

matching, in a first stage of the plurality of stages, the packet to a first plurality of field values and producing a first next stage identifier and a first offset value;

if the next stage identifier indicates a second stage, matching, in a second stage of the plurality of stages, the packet beginning at the first offset value to a second plurality of field values and producing a second next stage identifier and a second offset value;

if the first next stage identifier indicates a final stage, matching, in a final stage of the plurality of stages, the packet beginning at the first offset value to a final plurality of field values and producing an action identifier and a parameter value; and

if the second next stage identifier indicates a final stage, matching, in a final stage of the plurality of stages, the packet beginning at the second offset value to a final plurality of field values and producing an action identifier and a timing parameter.

26 . The method of claim 25 , further comprising extracting portions of the packet from at least some of the stages and combining the extracted portions to form a signature of the packet.

27 . The method of claim 25 , wherein matching comprises comparing portions of the packet to the plurality of field values corresponding to the stage and selecting a highest priority field value that matches.

28 . The method of claim 27 , wherein the comparing portions of the packet to the plurality of field values comprises arithmetic range comparisons.

29 . The method of claim 27 , wherein the comparing portions of the packet to the plurality of field values comprises bit-wise logical comparisons.

30 . The method of claim 27 , wherein the comparing portions of the packet to the plurality of field values comprises comparing multiple portions of the packet to a same one of the field values.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.), INC.; MICROSEMI FREQUENCY AND TIME CORPORATION; MICROSEMI COMMUNICATIONS, INC.; MICROSEMI SOC CORP.; MICROSEMI CORP. - POWER PRODUCTS GROUP; MICROSEMI CORP. - RF INTEGRATED SOLUTIONS
Reel/Frame 046251/0391 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC. (F/K/A LEGERITY, INC., ZARLINK SEMICONDUCTOR (V.N.) INC., CENTELLAX, INC., AND ZARLINK SEMICONDUCTOR (U.S.) INC.); MICROSEMI FREQUENCY AND TIME CORPORATION (F/K/A SYMMETRICON, INC.); MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION); MICROSEMI SOC CORP. (F/K/A ACTEL CORPORATION); MICROSEMI CORP. - POWER PRODUCTS GROUP (F/K/A ADVANCED POWER TECHNOLOGY INC.); MICROSEMI CORP. - RF INTEGRATED SOLUTIONS (F/K/A AML COMMUNICATIONS, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037691/0697 →
RELEASE OF SECURITY INTEREST Recorded Jan 19, 2016
From: BANK OF AMERICA, N.A.
To: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP, A DELAWARE CORPORATION; MICROSEMI SOC CORP., A CALIFORNIA CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC., A DELAWARE CORPORATION; MICROSEMI FREQUENCY AND TIME CORPORATION, A DELAWARE CORPORATION; MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION), A DELAWARE CORPORATION; MICROSEMI CORP.-MEMORY AND STORAGE SOLUTIONS (F/K/A WHITE ELECTRONIC DESIGNS CORPORATION), AN INDIANA CORPORATION
Reel/Frame 037558/0711 →
MERGER AND CHANGE OF NAME Recorded May 13, 2015
From: VITESSE SEMICONDUCTOR CORPORATION; LLIU100 ACQUISITION CORP.
To: MICROSEMI COMMUNICATIONS, INC.
Reel/Frame 035623/0632 →
SUPPLEMENTAL SECURITY AGREEMENT Recorded Apr 29, 2015
From: MICROSEMI COMMUNICATIONS, INC.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 035532/0925 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2015
From: SWARTZENTRUBER, RON; LOPOULOS, WILIAM D.
To: VITESSE SEMICONDUCTOR CORPORATION
Reel/Frame 035172/0242 →